ttc_parity Entity Reference

generate parity for data going from Control FPGA to Processors More...

Inheritance diagram for ttc_parity:

Entities
rtl	architecture
	generate parity for data going from Control FPGA to Processors More...

Libraries
ieee

Use Clauses
std_logic_1164

Generics
SEED	STD_LOGIC := ' 1 '

Ports
ttc_data	in	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
parity12	out	STD_LOGIC
parity32	out	STD_LOGIC

Detailed Description

generate parity for data going from Control FPGA to Processors

Outputs parity of 12 bit (BCN) and full 32 bit TTC word Odd or even depending on GENERIC SEED

Author

Dave Sankey

Definition at line 13 of file ttc_parity.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/ttc_parity.vhd