rtl Architecture Reference

generate parity for data going from Control FPGA to Processors More...

Signals
parity_calc	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
parity_merge	STD_LOGIC_VECTOR ( 7 DOWNTO 0 )

Detailed Description

generate parity for data going from Control FPGA to Processors

Outputs parity of 12 bit (BCN) and full 32 bit TTC word Odd or even depending on GENERIC SEED

Author

Dave Sankey

Definition at line 23 of file ttc_parity.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/ttc_parity.vhd