bcn_l1a_valid_checker.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library TOB_rdout_lib;
 
library infrastructure_lib;
 
entity bcn_l1a_valid_checker is
GENERIC(
    ILA_ENABLED         : std_logic := '0'
);
port(
    clk_40_i : in std_logic;
    rst_i : in std_logic; -- resets the counters
 
    l1a_id_ext_i : in std_logic_vector(31 downto 0);
    l1a_in_i : in std_logic;
    ecr_in_i : in std_logic;
    bcn_id_lcl_i : in std_logic_vector(11 downto 0);
    ttc_parity_i : in std_logic;
 
    err_history_o : out std_logic_vector(31 downto 0) := (others => '0');
    l1a_id_good_o : out std_logic_vector(31 downto 0) := (others => '0');
    l1a_id_err_o : out std_logic_vector(31 downto 0) := (others => '0');
    l1a_id_expected_o : out std_logic_vector(31 downto 0) := (others => '0');
    bcn_err_expected_o : out std_logic_vector(31 downto 0) := (others => '0');
    l1id_parity_err_cntr_o : out std_logic_vector(31 downto 0) := (others => '0');
    l1id_mismatch_cntr_o : out std_logic_vector(31 downto 0) := (others => '0');
    bcn_parity_err_cntr_o : out std_logic_vector(31 downto 0) := (others => '0');
    bcn_mismatch_cntr_o : out std_logic_vector(31 downto 0) := (others => '0')
    );
end bcn_l1a_valid_checker;
 
architecture rtl of bcn_l1a_valid_checker is
    signal probe_o : std_logic_vector(34 downto 0) := (others=>'0');
    signal l1id_next: std_logic_vector(31 downto 0) := (others => '0');
    signal bcn_err_trigger, bcn_mismatch_trigger, l1id_err_trigger, l1id_mismatch_trigger, parity12, parity32: std_logic;
 
    COMPONENT ila_1
    PORT (
       clk : IN STD_LOGIC;
       probe0 : IN STD_LOGIC_VECTOR(34 DOWNTO 0)
    );
    END COMPONENT;
begin
 
   ttc_parity_calc : entity infrastructure_lib.ttc_parity
      port map (
        ttc_data => l1a_id_ext_i,
        parity12 => parity12,
        parity32 => parity32
        );
 
-- next L1ID block: take incoming l1a_id_ext_i if parity OK, otherwise update local cache
    l1id_next_block: process(clk_40_i)
        variable l1id_local : unsigned(23 downto 0);
        variable ecrid_local : unsigned(7 downto 0);
        begin
            if rising_edge(clk_40_i) then
                if (rst_i = '1') then
                    ecrid_local := (Others => '0');
                    l1id_local := (Others => '0');
                else
                    if (l1a_in_i = '1') then
                        if (ttc_parity_i = parity32) then
                            ecrid_local := unsigned(l1a_id_ext_i(31 downto 24));
                            l1id_local := unsigned(l1a_id_ext_i(23 downto 0));
                        end if;
                        l1id_local := l1id_local + 1;
                    elsif (ecr_in_i = '1') then
                        if (ecrid_local = x"FF") then
                            ecrid_local := (Others => '0');
                        else
                            ecrid_local := ecrid_local + 1;
                        end if;
                        l1id_local := (Others => '0');
                    end if;
                end if;
                l1id_next <= std_logic_vector(ecrid_local & l1id_local);
            end if;
        end process l1id_next_block;
 
    -- makes sure relevant outputs are going to the ila
    debug_output : process (clk_40_i)
        variable parity_err_bcn, parity_err_l1id : std_logic := '0'; -- Will go high if it spots an error
        variable mismatch_bcn, mismatch_l1id : std_logic := '0'; -- Will go high if it spots an error
        variable err_history: std_logic_vector(31 downto 0) := (others => '0');
    begin
        if rising_edge(clk_40_i) then
            if (rst_i = '1') then
                parity_err_bcn := '0';
                parity_err_l1id := '0';
                mismatch_bcn := '0';
                mismatch_l1id := '0';
                err_history := (Others => '0');
 
                probe_o <= (Others => '0');
                l1a_id_good_o <= (Others => '0');
                l1a_id_err_o <= (Others => '0');
                l1a_id_expected_o <= (Others => '0');
                bcn_err_expected_o <= (Others => '0');
            else
                -- check incoming signal against expectations
                parity_err_bcn := '0';
                parity_err_l1id := '0';
                mismatch_bcn := '0';
                mismatch_l1id := '0';
                if (l1a_in_i = '0') then
                    if (ttc_parity_i /= parity12) then
                        parity_err_bcn := '1';
                    end if;
                    if (l1a_id_ext_i(11 downto 0) /= bcn_id_lcl_i) then
                        mismatch_bcn := '1';
                    end if;
                else
                    if (ttc_parity_i /= parity32) then
                        parity_err_l1id := '1';
                    end if;
                    if (l1a_id_ext_i /= l1id_next) then
                        mismatch_l1id := '1';
                    end if;
                end if;
 
                -- manages the rest of the output signals --
                if (parity_err_bcn = '1') or (mismatch_bcn = '1') then
                    err_history := err_history(27 downto 0) & parity_err_bcn & mismatch_bcn & "00";
                    bcn_err_expected_o <= parity_err_bcn & mismatch_bcn & "00" & bcn_id_lcl_i & "0000" & l1a_id_ext_i(11 downto 0);
                elsif (parity_err_l1id = '1') or (mismatch_l1id = '1') then
                    err_history := err_history(27 downto 0) & "00" & parity_err_l1id & mismatch_l1id;
                    l1a_id_err_o <= l1a_id_ext_i;
                    l1a_id_expected_o <= l1id_next;
                elsif (l1a_in_i = '1') then
                    l1a_id_good_o <= l1a_id_ext_i;
                end if;
 
                -- manages what output is going to the ila probe0 --
                if l1a_in_i = '1' then -- if l1a_in_i is active, l1a_id_ext_i is transmitting L1A ID, so examine that
                    -- sets probe output to look at L1A ID, as it is transmitted whilst l1a_in_i = '1'
                    probe_o <= parity_err_l1id & mismatch_l1id & l1a_in_i & l1a_id_ext_i;
                else -- when l1a_in is not active, l1a_id_ext_i is transmitting BCN ID, so examine that
                    -- sets probe output to look at BCN ID, as it is transmitted whilst l1a_in_i = '0'
                    probe_o <= parity_err_bcn & mismatch_bcn & l1a_in_i & "0000" & bcn_id_lcl_i & "0000" & l1a_id_ext_i(11 downto 0);
                end if;
            end if;
            bcn_err_trigger <= parity_err_bcn;
            bcn_mismatch_trigger <= mismatch_bcn;
            l1id_err_trigger <= parity_err_l1id;
            l1id_mismatch_trigger <= mismatch_l1id;
            err_history_o <= err_history;
        end if;
    end process debug_output;
 
    l1id_parity_err_cntr_block : entity TOB_rdout_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
        CE  => l1id_err_trigger,
        CLK => clk_40_i,
        RST => rst_i,
        Q   => l1id_parity_err_cntr_o);
 
    l1id_mismatch_cntr_block : entity TOB_rdout_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
        CE  => l1id_mismatch_trigger,
        CLK => clk_40_i,
        RST => rst_i,
        Q   => l1id_mismatch_cntr_o);
 
    bcn_parity_err_cntr_block : entity TOB_rdout_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
        CE  => bcn_err_trigger,
        CLK => clk_40_i,
        RST => rst_i,
        Q   => bcn_parity_err_cntr_o);
 
    bcn_mismatch_cntr_block : entity TOB_rdout_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
        CE  => bcn_mismatch_trigger,
        CLK => clk_40_i,
        RST => rst_i,
        Q   => bcn_mismatch_cntr_o);
 
ila_block : if (ILA_ENABLED = '1') generate
    debug_bcn_l1a_parity : ila_1
    PORT MAP (
       clk => clk_40_i,
       probe0 => probe_o
    );
end generate;
 
end rtl;