cntr_generic.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
 
entity cntr_generic is
    generic (
        width  : integer := 32;
        WRAPAROUND : boolean := True
        );
    Port (
       CE   : in STD_LOGIC;
       CLK  : in STD_LOGIC;
       RST  : in STD_LOGIC;
       Q    : out STD_LOGIC_VECTOR (width-1 downto 0)
       );
end cntr_generic;
 
architecture Behavioral of cntr_generic is
 
begin
process (CLK)
    variable temp : unsigned (width-1 downto 0);
    constant maxval: unsigned (width-1 downto 0) := (Others => '1');
    begin
    if CLK'event AND CLK = '1' then
        if RST = '1' then           -- this is a synchronous reset
            temp := (others => '0');              -- set counter to offset value given.
        else
          if (CE = '1') and (WRAPAROUND or (temp /= maxval)) then
             temp := temp + 1;                    -- else increment the value by one
          end if;
        end if;
    end if;
    Q <= std_logic_vector(temp) ;    -- push out new value
    end process;
 
end Behavioral;