src Directory Reference

Files
file	busy_flag_fsm.vhd [code]
	This module controls the BUSY Flag assert and de-assert.
file	clk_closs_pulse_fsm.vhd [code]
	This module accepts an input signal and generate a pulse for clock domain crossing.
file	cntr_generic.vhd [code]
	Generic Counter for process FPGA.
file	cntr_L1A_generic.vhd [code]
	24 bit Counter for L1A ID of process FPGA
file	cntr_ram_addr_10b.vhd [code]
	10b counter
file	cntr_ram_addr_9b.vhd [code]
	9b counter
file	cntr_up_dn_generic.vhd [code]
	Up/Down counter.
file	FIFO_to_MGT_RAW_FSM.vhd [code]
	FSM to read RAW Event data from Link Output FIFO to MGT for process FPGA.
file	FIFO_to_MGT_TOB_FSM.vhd [code]
	FSM to read TOB/XTOB data from Link Output FIFO for process FPGA.
file	fsm_extra_busy_en.vhd [code]
	Top of fsm_extra_busy_en for process FPGA.
file	fsm_RAW_data_wr_to_DPR.vhd [code]
	Transfer calorimeter data from Circular DPRAM to de-randomisation FIFO.
file	fsm_RAW_to_muxPISO.vhd [code]
	FSM to write RAW calolimeter data to Link Output FIFO for process FPGA.
file	fsm_TOB_double_word.vhd [code]
	Top of fsm_TOB_double_word for process FPGA.
file	fsm_TOB_wr_to_FIFO.vhd [code]
	Top of fsm_TOB_wr_to_FIFO for process FPGA.
file	fsm_TOBs_to_muxPISO.vhd [code]
	FSM to write Merged TOBs and Local XTOBs (tau & e/g) data to Link Output FIFO for process FPGA 1 and 2.
file	gen_sync_280M.vhd [code]
	Generate Synch at 280MHz.
file	link_errors_ORed.vhd [code]
	This is the RAW Data Error Flag Module.
file	PISO_RAW_data.vhd [code]
	Calorimeter data PISO for process FPGA.
file	RAW_data_rdout.vhd [code]
	RAW Calorimeter Data Readout Logic for process FPGA.
file	RAW_fifo_full_flag_gen.vhd [code]
	Generate Full Flag for RAW data de-randomisation FIFO.
file	readout_ipb_slave.vhd [code]
	IPBUS readout slave definitions of registers used in the Top Level Readout Block.
file	Readout_logic_top.vhd [code]
	Top Level of Readout Logic for process FPGA.
file	SIPO_TOPO_TOBs_unit.vhd [code]
	SIPO Sorting TOBs for process FPGA.
file	SIPO_unit.vhd [code]
	XTOB SIPO for process FPGA.
file	slave_RAW_readout.vhd [code]
	RAW calorimeter data readout slave registers.
file	slave_TOB_readout.vhd [code]
	TOB/XTOB data readout slave registers.
file	T_TOBs_sorting.vhd [code]
	Top of Sorting_TOBs module for process FPGA.
file	tide_mark_block.vhd [code]
	Instantiate tide mark calculation for a 16 bit data input.
file	TOBs_rdout.vhd [code]
	Merged Sorted TOB and Local XTOB Readout Logic for process FPGA.
file	XTOBs_sorting.vhd [code]
	Top of Sorting XTOBs module for process FPGA.