RAW_fifo_full_flag_gen.vhd File Reference

Generate Full Flag for RAW data de-randomisation FIFO. More...

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Entities
RAW_fifo_full_flag_gen	entity
	Generate Full Flag for RAW data de-randomisation FIFO. More...
Behavioral	architecture
	Generate Full Flag for RAW data de-randomisation FIFO. More...

Detailed Description

Generate Full Flag for RAW data de-randomisation FIFO.

This Module monitors the occupancy level of one de-randomisation FIFO for channel 20.

Channel 20 has been chosen in order to be in the middle of the FPGA, but any other channel can be selected.

The programmable Assert and Negate registers control the occupancy levels at which the FULL Flag is asserted and negated.

Therefore it generates Full Flag for RAW data de-randomisation FIFO by monitoring the data count

This flag has to be on a 7 word boundary (each input = 7 x 32-bit words), as for each L1A 7x32-bit words are transferred.

Author

Saeed Taghavi

Definition in file RAW_fifo_full_flag_gen.vhd.