RAW_fifo_full_flag_gen.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
 
entity RAW_fifo_full_flag_gen is
    Port (
       rst_in         : in STD_LOGIC;
       clk_in         : in STD_LOGIC;
       fifo_data_count    : in STD_LOGIC_VECTOR (8 downto 0);
       assert_count_in    : in STD_LOGIC_VECTOR (8 downto 0);
       negate_count_in    : in STD_LOGIC_VECTOR (8 downto 0);
       full_flag_out   : out STD_LOGIC    
       );
end RAW_fifo_full_flag_gen;
 
architecture Behavioral of RAW_fifo_full_flag_gen is
    
begin
  
U0: process (clk_in)
    begin 
    if (clk_in'event and clk_in = '1') then
        if (rst_in = '1') then
            full_flag_out <= '0' ;      -- set flag ZERO
        else
            if (unsigned(fifo_data_count) > unsigned(assert_count_in)) then  -- greater
                full_flag_out <= '1' ;      -- set full flag
            else
                if (unsigned(fifo_data_count) < unsigned(negate_count_in)) then -- smaller
                   full_flag_out <= '0' ;      -- set flag ZERO
                end if;
            end if;
        end if;
    end if;
    end process;
 
end Behavioral;