RAW_fifo_full_flag_gen Entity Reference

Generate Full Flag for RAW data de-randomisation FIFO. More...

Inheritance diagram for RAW_fifo_full_flag_gen:

Entities
Behavioral	architecture
	Generate Full Flag for RAW data de-randomisation FIFO. More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Ports
rst_in	in	STD_LOGIC
clk_in	in	STD_LOGIC
fifo_data_count	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		RAW FIFO data count input.
assert_count_in	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		assert count input to set Full Flag
negate_count_in	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		negate count input to set Full Flag
full_flag_out	out	STD_LOGIC
		Full Flag for RAW input FIFO.

Detailed Description

Generate Full Flag for RAW data de-randomisation FIFO.

This Module monitors the occupancy level of one de-randomisation FIFO for channel 20.

Channel 20 has been chosen in order to be in the middle of the FPGA, but any other channel can be selected.

The programmable Assert and Negate registers control the occupancy levels at which the FULL Flag is asserted and negated.

Therefore it generates Full Flag for RAW data de-randomisation FIFO by monitoring the data count

This flag has to be on a 7 word boundary (each input = 7 x 32-bit words), as for each L1A 7x32-bit words are transferred.

Author

Saeed Taghavi

Definition at line 25 of file RAW_fifo_full_flag_gen.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/RAW_fifo_full_flag_gen.vhd