fsm_extra_busy_en.vhd File Reference

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Entities
fsm_extra_busy_en	entity
	Top of fsm_extra_busy_en for process FPGA. More...
Behavioral	architecture
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Detailed Description

Top of fsm_extra_busy_en for process FPGA.

This state machine is responsible for providing enable signal to all BUSY counters After a reset, an extra enable is provided to ensure the counter goes to '1' after an enable signal.

It also controls multi-slice readout between 1 to 5 slices in sequence.

Author

Saeed Taghavi

Definition in file fsm_extra_busy_en.vhd.