fsm_extra_busy_en Entity Reference

Top of fsm_extra_busy_en for process FPGA. More...

Entities
Behavioral	architecture
	Top of fsm_extra_busy_en for process FPGA. More...

Libraries
IEEE
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>

Ports
CLK_IN	in	STD_LOGIC
		Clock input signal.
busy_counter_rst	in	std_logic
		busy counter reset signal from IPBUS
RST	in	STD_LOGIC
		power up reset
busy_extra_en_out	out	STD_LOGIC
		enable signal to all BUSY counters

Detailed Description

Top of fsm_extra_busy_en for process FPGA.

This state machine is responsible for providing enable signal to all BUSY counters After a reset, an extra enable is provided to ensure the counter goes to '1' after an enable signal.

It also controls multi-slice readout between 1 to 5 slices in sequence.

Author

Saeed Taghavi

Definition at line 22 of file fsm_extra_busy_en.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/fsm_extra_busy_en.vhd