Behavioral Architecture Reference

Top of fsm_extra_busy_en for process FPGA. More...

Processes
U3_rd_XTOB_fsm	( CLK_IN )

Types
STATE_TYPE	( idle , ser_1 , ser_2 , ser_3 , ser_4 )

Signals
busy_en_out_i	std_logic
current_state	STATE_TYPE

Detailed Description

Top of fsm_extra_busy_en for process FPGA.

This state machine is responsible for providing enable signal to all BUSY counters After a reset, an extra enable is provided to ensure the counter goes to '1' after an enable signal.

It also controls multi-slice readout between 1 to 5 slices in sequence.

Author

Saeed Taghavi

Definition at line 36 of file fsm_extra_busy_en.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/fsm_extra_busy_en.vhd