eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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slave_RAW_readout.vhd
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1 
6 
32 
33 library IEEE;
34 use IEEE.STD_LOGIC_1164.all;
35 
36 library ipbus_lib;
37 use ipbus_lib.ipbus.all;
38 
39 library TOB_rdout_lib;
40 use TOB_rdout_lib.data_type_pkg.all;
41 use TOB_rdout_lib.ipbus_decode_efex_raw_readout.all; -- RAW calorimeter readout package
42 
44 entity slave_RAW_readout is
45  port (
47  ipb_rst : in std_logic;
49  ipb_clk : in std_logic;
51  IPb_in : in ipb_wbus; -- The signals going from master to slaves
53  IPb_out : out ipb_rbus; -- The signals going from slaves to master
54 
56  RAW_FIFO_pFULL_THRESH_ASSERT : out std_logic_vector(8 downto 0);
58  RAW_FIFO_pFULL_THRESH_NEGATE : out std_logic_vector(8 downto 0);
59 
61  BCN_FIFO_pFULL_THRESH_assert : out std_logic_vector(8 downto 0);
63  BCN_FIFO_pFULL_THRESH_negate : out std_logic_vector(8 downto 0);
65  BCN_FIFO_RAW_rd_data_count : in STD_LOGIC_VECTOR (31 downto 0); -- occupancy of BCN & L1A FIFO for RAW Readout
66 
68  Link_output_FIFO_pFULL_THRESH_ASSERT : out std_logic_vector (12 downto 0);
70  Link_output_FIFO_pFULL_THRESH_NEGATE : out std_logic_vector (12 downto 0);
72  Link_output_FIFO_rd_data_count : in std_logic_vector (31 downto 0);
74  RAW_frame_count : in std_logic_vector (31 downto 0);
75 
77  RAW_FIFO_FULL_THRESH_ASSERT : out std_logic_vector(8 downto 0);
79  RAW_FIFO_FULL_THRESH_NEGATE : out std_logic_vector(8 downto 0);
81  RAW_FIFO_data_count : in std_logic_vector(31 downto 0);
83  raw_busy_thresh_assert : out STD_LOGIC_VECTOR (8 downto 0); -- TOBs FIFO
85  raw_busy_thresh_negate : out STD_LOGIC_VECTOR (8 downto 0); -- TOBs FIFO
86 
88  RAW_data_FIFO_flags : in std_logic_vector (31 downto 0);
90  RAW_WR_ADDR_OFFSET : out std_logic_vector (9 downto 0);
92  SPY_RAW_mem_wr_addr : in std_logic_vector (10 downto 0);
94  ipbus_out_raw_dpram : out ipb_wbus; -- signal going to RAW SPY DPRAM
96  ipbus_in_raw_dpram : in ipb_rbus; -- signal coming from RAW SPY DPRAM
98  link_error_flags : in STD_LOGIC_VECTOR (53 downto 0);
100  raw_fsm_monitor : in std_logic_vector (31 downto 0)
101  );
102 end slave_RAW_readout;
103 
105 architecture Behavioral of slave_RAW_readout is
106  signal ipbw : ipb_wbus_array(N_SLAVES-1 downto 0);
107  signal ipbr, ipbr_d : ipb_rbus_array(N_SLAVES-1 downto 0);
108 
109  signal RAW_FIFO_pFULL_THRESH_ASSERT_i : std_logic_vector (31 downto 0);
110  signal RAW_FIFO_pFULL_THRESH_NEGATE_i : std_logic_vector (31 downto 0);
111 
112  signal BCN_FIFO_pFULL_THRESH_assert_i : std_logic_vector (31 downto 0);
113  signal BCN_FIFO_pFULL_THRESH_negate_i : std_logic_vector (31 downto 0);
114 
115  signal Link_output_FIFO_pFULL_THRESH_ASSERT_i : std_logic_vector (31 downto 0);
116  signal Link_output_FIFO_pFULL_THRESH_NEGATE_i : std_logic_vector (31 downto 0);
117 
118  signal RAW_FIFO_FULL_THRESH_ASSERT_i : std_logic_vector (31 downto 0);
119  signal RAW_FIFO_FULL_THRESH_NEGATE_i : std_logic_vector (31 downto 0);
120  signal BCN_FIFO_RAW_rd_data_count_i : std_logic_vector (31 downto 0);
121  signal raw_busy_thresh_assert_i : STD_LOGIC_VECTOR(31 downto 0);
122  signal raw_busy_thresh_negate_i : STD_LOGIC_VECTOR(31 downto 0);
123 
124  signal RAW_Link_output_FIFO_rd_data_count_i : std_logic_vector (31 downto 0);
125  signal RAW_data_FIFO_flags_i : std_logic_vector (31 downto 0);
126  signal RAW_FIFO_data_count_i : std_logic_vector (31 downto 0);
127  signal SPY_mem_wr_addr_i : std_logic_vector (31 downto 0);
128  signal RAW_WR_ADDR_OFFSET_REG_i : std_logic_vector (31 downto 0);
129  signal link_error_flags_1 : std_logic_vector (31 downto 0);
130  signal link_error_flags_2 : std_logic_vector (31 downto 0);
131 
132 begin
133  -- input signals
134  RAW_Link_output_FIFO_rd_data_count_i <= Link_output_FIFO_rd_data_count; -- 32 bits
135  RAW_FIFO_data_count_i <= RAW_FIFO_data_count; -- 32 bits
136  RAW_data_FIFO_flags_i <= RAW_data_FIFO_flags; -- 32 bits
137  BCN_FIFO_RAW_rd_data_count_i <= BCN_FIFO_RAW_rd_data_count; -- 32b
138 
139  SPY_mem_wr_addr_i <= X"00000" & "0" & SPY_RAW_mem_wr_addr;
140 
141  -- output signals
142  RAW_FIFO_pFULL_THRESH_ASSERT <= RAW_FIFO_pFULL_THRESH_ASSERT_i(8 downto 0);
143  RAW_FIFO_pFULL_THRESH_NEGATE <= RAW_FIFO_pFULL_THRESH_NEGATE_i(8 downto 0);
144 
145  raw_busy_thresh_assert <= raw_busy_thresh_assert_i(8 downto 0);
146  raw_busy_thresh_negate <= raw_busy_thresh_negate_i(8 downto 0);
147 
148  BCN_FIFO_pFULL_THRESH_assert <= BCN_FIFO_pFULL_THRESH_assert_i(8 downto 0);
149  BCN_FIFO_pFULL_THRESH_negate <= BCN_FIFO_pFULL_THRESH_negate_i(8 downto 0);
150 
151  Link_output_FIFO_pFULL_THRESH_ASSERT <= Link_output_FIFO_pFULL_THRESH_ASSERT_i(12 downto 0);
152  Link_output_FIFO_pFULL_THRESH_NEGATE <= Link_output_FIFO_pFULL_THRESH_NEGATE_i(12 downto 0);
153 
154  RAW_FIFO_FULL_THRESH_ASSERT <= RAW_FIFO_FULL_THRESH_ASSERT_i(8 downto 0);
155  RAW_FIFO_FULL_THRESH_NEGATE <= RAW_FIFO_FULL_THRESH_NEGATE_i(8 downto 0);
156 
157  RAW_WR_ADDR_OFFSET <= RAW_WR_ADDR_OFFSET_REG_i(9 downto 0);
158 
159  link_error_flags_1 <= link_error_flags(31 downto 0);
160  link_error_flags_2 <= "00000000000" & link_error_flags(53) & link_error_flags(51 downto 32); -- 4-b error = zero + input_crc + input_disparity + not_in_table
161 
162 ---- access to RAW DPRAM spy memeory
163  ipbus_out_raw_dpram <= ipbw(N_SLV_CALO_DATA_SPY_MEM); -- signal going to RAW SPY DPRAM
164  ipbr(N_SLV_CALO_DATA_SPY_MEM) <= ipbus_in_raw_dpram; -- signal coming from RAW SPY DPRAM
165 
171  RAW_rdout_fabric : entity ipbus_lib.ipbus_fabric_sel
172  generic map(NSLV => N_SLAVES,
173  SEL_WIDTH => ipbus_sel_width)
174  port map(
175  ipb_in => ipb_in,
176  ipb_out => ipb_out,
177  sel => ipbus_sel_efex_raw_readout(ipb_in.ipb_addr),
178  ipb_to_slaves => ipbw,
179  ipb_from_slaves => ipbr
180  );
181 
186  U1_RAW_FIFO_pFULL_THRESH_ASSERT : entity ipbus_lib.ipbus_ctrlreg_v
187  generic map(N_CTRL => 1, N_STAT => 0)
188  port map(
189  clk => ipb_clk,
190  reset => ipb_rst,
191  ipbus_in => ipbw(N_SLV_RAW_FIFO_PROG_FULL_THRESH_ASSERT),
192  ipbus_out => ipbr(N_SLV_RAW_FIFO_PROG_FULL_THRESH_ASSERT),
193  d => (others => (others => '0')),
194  q(0) => RAW_FIFO_pFULL_THRESH_ASSERT_i, -- read/write reg
195  ctrl_default(0) => X"00000180", -- optional port for non-zero default value
196  stb => open);
197 
198  U2_RAW_FIFO_pFULL_THRESH_NEGATE : entity ipbus_lib.ipbus_ctrlreg_v
199  generic map(N_CTRL => 1, N_STAT => 0)
200  port map(
201  clk => ipb_clk,
202  reset => ipb_rst,
203  ipbus_in => ipbw(N_SLV_RAW_FIFO_PROG_FULL_THRESH_NEGATE),
204  ipbus_out => ipbr(N_SLV_RAW_FIFO_PROG_FULL_THRESH_NEGATE),
205  d => (others => (others => '0')),
206  q(0) => RAW_FIFO_pFULL_THRESH_NEGATE_i, -- read/write reg
207  ctrl_default(0) => X"00000100", -- optional port for non-zero default value
208  stb => open);
209 
210 -- RAW BUSY flag assertion level
211 U3_RAW_BUSY_THRESH_ASSERT : entity ipbus_lib.ipbus_ctrlreg_v
212  generic map (
213  N_CTRL => 1, --number of control reg
214  N_STAT => 0) --number of status reg
215  port map (
216  clk => ipb_clk,
217  reset => ipb_rst,
218  ipbus_in => ipbw(N_SLV_RAW_BUSY_THRESH_ASSERT),
219  ipbus_out => ipbr(N_SLV_RAW_BUSY_THRESH_ASSERT),
220  d => (others=> (others=> '0')),
221  ctrl_default(0) => X"00000160", -- optional port for non-zero default value
222  q(0) => (raw_busy_thresh_assert_i),
223  stb => open
224  );
225 
226 -- RAW BUSY flag negation level
227 U3_RAW_BUSY_THRESH_NEGATE : entity ipbus_lib.ipbus_ctrlreg_v
228  generic map (
229  N_CTRL => 1, --number of control reg
230  N_STAT => 0) --number of status reg
231  port map (
232  clk => ipb_clk,
233  reset => ipb_rst,
234  ipbus_in => ipbw(N_SLV_RAW_BUSY_THRESH_NEGATE),
235  ipbus_out => ipbr(N_SLV_RAW_BUSY_THRESH_NEGATE),
236  d => (others=> (others=> '0')),
237  ctrl_default(0) => X"00000100", -- optional port for non-zero default value
238  q(0) => (raw_busy_thresh_negate_i),
239  stb => open
240  );
241 
242  U5_BCN_FIFO_pFULL_THRESH_assert : entity ipbus_lib.ipbus_ctrlreg_v
243  generic map(N_CTRL => 1, N_STAT => 0)
244  port map(
245  clk => ipb_clk,
246  reset => ipb_rst,
247  ipbus_in => ipbw(N_SLV_BCN_FIFO_PROG_FULL_THRESH_ASSERT),
248  ipbus_out => ipbr(N_SLV_BCN_FIFO_PROG_FULL_THRESH_ASSERT),
249  d => (others => (others => '0')),
250  q(0) => BCN_FIFO_pFULL_THRESH_assert_i, -- read/write reg
251  ctrl_default(0) => X"00000180", -- optional port for non-zero default value
252  stb => open);
253 
254  U6_BCN_FIFO_pFULL_THRESH_negate : entity ipbus_lib.ipbus_ctrlreg_v
255  generic map(N_CTRL => 1, N_STAT => 0)
256  port map(
257  clk => ipb_clk,
258  reset => ipb_rst,
259  ipbus_in => ipbw(N_SLV_BCN_FIFO_PROG_FULL_THRESH_NEGATE),
260  ipbus_out => ipbr(N_SLV_BCN_FIFO_PROG_FULL_THRESH_NEGATE),
261  d => (others => (others => '0')),
262  q(0) => BCN_FIFO_pFULL_THRESH_negate_i, -- read/write reg
263  ctrl_default(0) => X"00000100", -- optional port for non-zero default value
264  stb => open);
265 
266 -- BCN & L1A FIFO occupancy for RAW Readout
267  U6_BCN_FIFO_RAW_rd_data_count : entity ipbus_lib.ipbus_ctrlreg_v
268  generic map(N_CTRL => 0, N_STAT => 1)
269  port map(
270  clk => ipb_clk,
271  reset => ipb_rst,
272  ipbus_in => ipbw(N_SLV_BCN_FIFO_RAW_RD_DATA_COUNT),
273  ipbus_out => ipbr(N_SLV_BCN_FIFO_RAW_RD_DATA_COUNT),
274  d(0) => BCN_FIFO_RAW_rd_data_count_i, -- read only reg
275  q => open,
276  stb => open);
277 
278  U7_Link_output_FIFO_pFULL_THRESH_ASSERT : entity ipbus_lib.ipbus_ctrlreg_v
279  generic map(N_CTRL => 1, N_STAT => 0)
280  port map(
281  clk => ipb_clk,
282  reset => ipb_rst,
283  ipbus_in => ipbw(N_SLV_LINK_OUTPUT_FIFO_PROG_FULL_THRESH_ASSERT),
284  ipbus_out => ipbr(N_SLV_LINK_OUTPUT_FIFO_PROG_FULL_THRESH_ASSERT),
285  d => (others => (others => '0')),
286  q(0) => Link_output_FIFO_pFULL_THRESH_ASSERT_i, -- read/write reg
287  ctrl_default(0) => X"00001800", -- optional port for non-zero default value
288  stb => open);
289 
290  U8_Link_output_FIFO_pFULL_THRESH_NEGATE : entity ipbus_lib.ipbus_ctrlreg_v
291  generic map(N_CTRL => 1, N_STAT => 0)
292  port map(
293  clk => ipb_clk,
294  reset => ipb_rst,
295  ipbus_in => ipbw(N_SLV_LINK_OUTPUT_FIFO_PROG_FULL_THRESH_NEGATE),
296  ipbus_out => ipbr(N_SLV_LINK_OUTPUT_FIFO_PROG_FULL_THRESH_NEGATE),
297  d => (others => (others => '0')),
298  q(0) => Link_output_FIFO_pFULL_THRESH_NEGATE_i, -- read/write reg
299  ctrl_default(0) => X"00001000", -- optional port for non-zero default value
300  stb => open);
301 
306  U9_Link_output_FIFO_RD_DATA_COUNT : entity ipbus_lib.ipbus_ctrlreg_v
307  generic map(N_CTRL => 0, N_STAT => 1)
308  port map(
309  clk => ipb_clk,
310  reset => ipb_rst,
311  ipbus_in => ipbw(N_SLV_LINK_OUTPUT_FIFO_RD_DATA_COUNT),
312  ipbus_out => ipbr(N_SLV_LINK_OUTPUT_FIFO_RD_DATA_COUNT),
313  d(0) => RAW_Link_output_FIFO_rd_data_count_i, -- read only reg
314  q => open,
315  stb => open);
316 
317  U9A_RAW_FIFO_FULL_THRESH_ASSERT : entity ipbus_lib.ipbus_ctrlreg_v
318  generic map(N_CTRL => 1, N_STAT => 0)
319  port map(
320  clk => ipb_clk,
321  reset => ipb_rst,
322  ipbus_in => ipbw(N_SLV_RAW_FIFO_FULL_THRESH_ASSERT),
323  ipbus_out => ipbr(N_SLV_RAW_FIFO_FULL_THRESH_ASSERT),
324  q(0) => RAW_FIFO_FULL_THRESH_ASSERT_i, -- read/write reg
325  d => (others => (others => '0')),
326  ctrl_default(0) => X"000001A0", -- optional port for non-zero default value
327  stb => open);
328 
329  U9B_RAW_FIFO_FULL_THRESH_NEGATE : entity ipbus_lib.ipbus_ctrlreg_v
330  generic map(N_CTRL => 1, N_STAT => 0)
331  port map(
332  clk => ipb_clk,
333  reset => ipb_rst,
334  ipbus_in => ipbw(N_SLV_RAW_FIFO_FULL_THRESH_NEGATE),
335  ipbus_out => ipbr(N_SLV_RAW_FIFO_FULL_THRESH_NEGATE),
336  q(0) => RAW_FIFO_FULL_THRESH_NEGATE_i, -- read/write reg
337  d => (others => (others => '0')),
338  ctrl_default(0) => X"00000100", -- optional port for non-zero default value
339  stb => open);
340 
341  U9C_RAW_FIFO_data_count : entity ipbus_lib.ipbus_ctrlreg_v
342  generic map(N_CTRL => 0, N_STAT => 1)
343  port map(
344  clk => ipb_clk,
345  reset => ipb_rst,
346  ipbus_in => ipbw(N_SLV_RAW_FIFO_DATA_COUNT),
347  ipbus_out => ipbr(N_SLV_RAW_FIFO_DATA_COUNT),
348  d(0) => RAW_FIFO_data_count_i, -- read only reg
349  q => open,
350  stb => open);
351 
352  U11_RAW_frame_count : entity ipbus_lib.ipbus_ctrlreg_v
353  generic map(N_CTRL => 0, N_STAT => 1)
354  port map(
355  clk => ipb_clk,
356  reset => ipb_rst,
357  ipbus_in => ipbw(N_SLV_RAW_FRAME_COUNT),
358  ipbus_out => ipbr(N_SLV_RAW_FRAME_COUNT),
359  d(0) => RAW_frame_count, -- read only reg
360  q => open,
361  stb => open);
362 
363  U12_RAW_data_FIFO_flags : entity ipbus_lib.ipbus_ctrlreg_v
364  generic map(N_CTRL => 0, N_STAT => 1)
365  port map(
366  clk => ipb_clk,
367  reset => ipb_rst,
368  ipbus_in => ipbw(N_SLV_RAW_DATA_FIFO_FLAGS),
369  ipbus_out => ipbr(N_SLV_RAW_DATA_FIFO_FLAGS),
370  d(0) => RAW_data_FIFO_flags_i, -- read only reg
371  q => open,
372  stb => open);
373 
374  U13_SPY_mem_wr_addr : entity ipbus_lib.ipbus_ctrlreg_v
375  generic map(N_CTRL => 0, N_STAT => 1)
376  port map(
377  clk => ipb_clk,
378  reset => ipb_rst,
379  ipbus_in => ipbw(N_SLV_SPY_MEM_WR_ADDR),
380  ipbus_out => ipbr(N_SLV_SPY_MEM_WR_ADDR),
381  d(0) => SPY_mem_wr_addr_i, -- read only reg
382  q => open,
383  stb => open);
384 
385  U15_RAW_WR_ADDR_OFFSET_REG : entity ipbus_lib.ipbus_ctrlreg_v
386  generic map(N_CTRL => 1, N_STAT => 0)
387  port map(
388  clk => ipb_clk,
389  reset => ipb_rst,
390  ipbus_in => ipbw(N_SLV_RAW_WR_ADDR_OFFSET_REG),
391  ipbus_out => ipbr(N_SLV_RAW_WR_ADDR_OFFSET_REG),
392  q(0) => RAW_WR_ADDR_OFFSET_REG_i, -- read/write reg
393  d => (others => (others => '0')),
394  stb => open);
395 
396  U16_FIFO_LINK_ERRORS : entity ipbus_lib.ipbus_ctrlreg_v
397  generic map(N_CTRL => 0, N_STAT => 2)
398  port map(
399  clk => ipb_clk,
400  reset => ipb_rst,
401  ipbus_in => ipbw(N_SLV_FIFO_LINK_ERRORS),
402  ipbus_out => ipbr(N_SLV_FIFO_LINK_ERRORS),
403  d(0) => link_error_flags_1, -- read only reg
404  d(1) => link_error_flags_2, -- read only reg
405  q => open,
406  stb => open);
407 
408  U17_raw_fsm_monitor : entity ipbus_lib.ipbus_ctrlreg_v
409  generic map(N_CTRL => 0, N_STAT => 1)
410  port map(
411  clk => ipb_clk,
412  reset => ipb_rst,
413  ipbus_in => ipbw(N_SLV_RAW_FSM_MONITOR),
414  ipbus_out => ipbr(N_SLV_RAW_FSM_MONITOR),
415  d(0) => raw_fsm_monitor, -- read only reg
416  q => open,
417  stb => open);
418 
419 
420 end Behavioral;
data_type_pkg
Definition: data_type_pkg.vhd:34
slave_RAW_readout.Behavioral
RAW calorimeter data readout slave registers.
Definition: slave_RAW_readout.vhd:105
slave_RAW_readout
RAW calorimeter data readout slave registers.
Definition: slave_RAW_readout.vhd:44
slave_RAW_readout.BCN_FIFO_RAW_rd_data_count
in BCN_FIFO_RAW_rd_data_count STD_LOGIC_VECTOR( 31 downto 0)
BCN & L1A FIFO occupancy for RAW Readout.
Definition: slave_RAW_readout.vhd:65
slave_RAW_readout.RAW_FIFO_data_count
in RAW_FIFO_data_count std_logic_vector( 31 downto 0)
Derandomisation FIFO FIFO occupancy data count.
Definition: slave_RAW_readout.vhd:81
slave_RAW_readout.Link_output_FIFO_pFULL_THRESH_ASSERT
out Link_output_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 12 downto 0)
Link output FIFO (before MGT) partial full flag assert threshold.
Definition: slave_RAW_readout.vhd:68
slave_RAW_readout.ipb_rst
in ipb_rst std_logic
IPBus Reset input.
Definition: slave_RAW_readout.vhd:47
slave_RAW_readout.RAW_WR_ADDR_OFFSET
out RAW_WR_ADDR_OFFSET std_logic_vector( 9 downto 0)
The write address offset pre load for RAW data Circular DRPAM.
Definition: slave_RAW_readout.vhd:90
slave_RAW_readout.raw_busy_thresh_assert
out raw_busy_thresh_assert STD_LOGIC_VECTOR( 8 downto 0)
raw BUSY flag threshold assert
Definition: slave_RAW_readout.vhd:83
slave_RAW_readout.Link_output_FIFO_pFULL_THRESH_NEGATE
out Link_output_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 12 downto 0)
Link output FIFO (before MGT) partial full flag negate threshold.
Definition: slave_RAW_readout.vhd:70
slave_RAW_readout.IPb_out
out IPb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: slave_RAW_readout.vhd:53
slave_RAW_readout.Link_output_FIFO_rd_data_count
in Link_output_FIFO_rd_data_count std_logic_vector( 31 downto 0)
Link output FIFO (before MGT) occupancy data count.
Definition: slave_RAW_readout.vhd:72
slave_RAW_readout.raw_busy_thresh_negate
out raw_busy_thresh_negate STD_LOGIC_VECTOR( 8 downto 0)
raw BUSY flag threshold de-assert
Definition: slave_RAW_readout.vhd:85
slave_RAW_readout.RAW_data_FIFO_flags
in RAW_data_FIFO_flags std_logic_vector( 31 downto 0)
Read only register containing all Empty pFull and Full of RAW data block.
Definition: slave_RAW_readout.vhd:88
slave_RAW_readout.RAW_frame_count
in RAW_frame_count std_logic_vector( 31 downto 0)
numer of frames in the link output FIFO to be transmitted to MGT & Control FPGA
Definition: slave_RAW_readout.vhd:74
slave_RAW_readout.IPb_in
in IPb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: slave_RAW_readout.vhd:51
slave_RAW_readout.link_error_flags
in link_error_flags STD_LOGIC_VECTOR( 53 downto 0)
54-b error flags from the Error Flag FIFO to IPBUS register
Definition: slave_RAW_readout.vhd:98
slave_RAW_readout.ipb_clk
in ipb_clk std_logic
IPBus Clock input.
Definition: slave_RAW_readout.vhd:49
slave_RAW_readout.SPY_RAW_mem_wr_addr
in SPY_RAW_mem_wr_addr std_logic_vector( 10 downto 0)
RAW SPY Memory write address (read only register)
Definition: slave_RAW_readout.vhd:92
slave_RAW_readout.RAW_FIFO_FULL_THRESH_NEGATE
out RAW_FIFO_FULL_THRESH_NEGATE std_logic_vector( 8 downto 0)
36b derandomisation FIFO full flag negate threshold
Definition: slave_RAW_readout.vhd:79
slave_RAW_readout.RAW_FIFO_pFULL_THRESH_ASSERT
out RAW_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 8 downto 0)
Derandomisation FIFO partial full flag assert threshold.
Definition: slave_RAW_readout.vhd:56
slave_RAW_readout.BCN_FIFO_pFULL_THRESH_negate
out BCN_FIFO_pFULL_THRESH_negate std_logic_vector( 8 downto 0)
BCN FIFO partial full flag negate threshold.
Definition: slave_RAW_readout.vhd:63
slave_RAW_readout.BCN_FIFO_pFULL_THRESH_assert
out BCN_FIFO_pFULL_THRESH_assert std_logic_vector( 8 downto 0)
BCN FIFO partial full flag assert threshold.
Definition: slave_RAW_readout.vhd:61
slave_RAW_readout.ipbus_out_raw_dpram
out ipbus_out_raw_dpram ipb_wbus
IPBus signal going to RAW SPY DPRAM.
Definition: slave_RAW_readout.vhd:94
slave_RAW_readout.RAW_FIFO_FULL_THRESH_ASSERT
out RAW_FIFO_FULL_THRESH_ASSERT std_logic_vector( 8 downto 0)
Derandomisation FIFO full flag assert threshold.
Definition: slave_RAW_readout.vhd:77
slave_RAW_readout.RAW_FIFO_pFULL_THRESH_NEGATE
out RAW_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 8 downto 0)
36b derandomisation FIFO partial full flag negate threshold
Definition: slave_RAW_readout.vhd:58
slave_RAW_readout.ipbus_in_raw_dpram
in ipbus_in_raw_dpram ipb_rbus
IPBus signal coming from RAW SPY DPRAM.
Definition: slave_RAW_readout.vhd:96
slave_RAW_readout.raw_fsm_monitor
in raw_fsm_monitor std_logic_vector( 31 downto 0)
Monitor RAW Readout state machines.
Definition: slave_RAW_readout.vhd:101
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