Behavioral Architecture Reference

RAW calorimeter data readout slave registers. More...

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ipbr_d	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
RAW_FIFO_pFULL_THRESH_ASSERT_i	std_logic_vector ( 31 downto 0 )
RAW_FIFO_pFULL_THRESH_NEGATE_i	std_logic_vector ( 31 downto 0 )
BCN_FIFO_pFULL_THRESH_assert_i	std_logic_vector ( 31 downto 0 )
BCN_FIFO_pFULL_THRESH_negate_i	std_logic_vector ( 31 downto 0 )
Link_output_FIFO_pFULL_THRESH_ASSERT_i	std_logic_vector ( 31 downto 0 )
Link_output_FIFO_pFULL_THRESH_NEGATE_i	std_logic_vector ( 31 downto 0 )
RAW_FIFO_FULL_THRESH_ASSERT_i	std_logic_vector ( 31 downto 0 )
RAW_FIFO_FULL_THRESH_NEGATE_i	std_logic_vector ( 31 downto 0 )
BCN_FIFO_RAW_rd_data_count_i	std_logic_vector ( 31 downto 0 )
raw_busy_thresh_assert_i	STD_LOGIC_VECTOR ( 31 downto 0 )
raw_busy_thresh_negate_i	STD_LOGIC_VECTOR ( 31 downto 0 )
RAW_Link_output_FIFO_rd_data_count_i	std_logic_vector ( 31 downto 0 )
RAW_data_FIFO_flags_i	std_logic_vector ( 31 downto 0 )
RAW_FIFO_data_count_i	std_logic_vector ( 31 downto 0 )
SPY_mem_wr_addr_i	std_logic_vector ( 31 downto 0 )
RAW_WR_ADDR_OFFSET_REG_i	std_logic_vector ( 31 downto 0 )
link_error_flags_1	std_logic_vector ( 31 downto 0 )
link_error_flags_2	std_logic_vector ( 31 downto 0 )

Instantiations
raw_rdout_fabric	ipbus_fabric_sel
u1_raw_fifo_pfull_thresh_assert	ipbus_ctrlreg_v
u2_raw_fifo_pfull_thresh_negate	ipbus_ctrlreg_v
u3_raw_busy_thresh_assert	ipbus_ctrlreg_v
u3_raw_busy_thresh_negate	ipbus_ctrlreg_v
u5_bcn_fifo_pfull_thresh_assert	ipbus_ctrlreg_v
u6_bcn_fifo_pfull_thresh_negate	ipbus_ctrlreg_v
u6_bcn_fifo_raw_rd_data_count	ipbus_ctrlreg_v
u7_link_output_fifo_pfull_thresh_assert	ipbus_ctrlreg_v
u8_link_output_fifo_pfull_thresh_negate	ipbus_ctrlreg_v
u9_link_output_fifo_rd_data_count	ipbus_ctrlreg_v
u9a_raw_fifo_full_thresh_assert	ipbus_ctrlreg_v
u9b_raw_fifo_full_thresh_negate	ipbus_ctrlreg_v
u9c_raw_fifo_data_count	ipbus_ctrlreg_v
u11_raw_frame_count	ipbus_ctrlreg_v
u12_raw_data_fifo_flags	ipbus_ctrlreg_v
u13_spy_mem_wr_addr	ipbus_ctrlreg_v
u15_raw_wr_addr_offset_reg	ipbus_ctrlreg_v
u16_fifo_link_errors	ipbus_ctrlreg_v
u17_raw_fsm_monitor	ipbus_ctrlreg_v

Detailed Description

RAW calorimeter data readout slave registers.

This module provides IPBus access for all Read Only and Read/Write reigsters withing the RAW calorimeter readout block. Function of modules/registers are listed in the same order as VHDL code.

Definition at line 105 of file slave_RAW_readout.vhd.

Member Data Documentation

raw_rdout_fabric

raw_rdout_fabric ipbus_fabric_sel

Instantiation

 The IPBus bus fabric, which also has address select logic and data multiplexers.
 This version selects the addressed slave depending on the state of incoming control lines.

Definition at line 180 of file slave_RAW_readout.vhd.

u1_raw_fifo_pfull_thresh_assert

u1_raw_fifo_pfull_thresh_assert ipbus_ctrlreg_v

Instantiation

 This is one 32b register, which is read and write cable through the IPBus.

Definition at line 196 of file slave_RAW_readout.vhd.

u9_link_output_fifo_rd_data_count

u9_link_output_fifo_rd_data_count ipbus_ctrlreg_v

Instantiation

 This is one 32b register, which is read only cable through the IPBus.

Definition at line 315 of file slave_RAW_readout.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/slave_RAW_readout.vhd