cntr_ram_addr_10b.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
 
entity cntr_ram_addr_10b is
    Port ( 
       CE     : in STD_LOGIC;
       CLK    : in STD_LOGIC;
       RST    : in STD_LOGIC;
       Q      : out STD_LOGIC_VECTOR (9 downto 0)
       );
    end cntr_ram_addr_10b;
 
architecture Behavioral of cntr_ram_addr_10b is
 
begin
process (CLK)
    variable temp  : unsigned (9 downto 0) ;
    begin
 
    if CLK'event AND CLK = '1' then
        if RST = '1' then           -- this is a synchronous reset
           temp := (others => '0') ;          -- set counter to zero
        else 
           if CE = '1' then
              temp := temp + 1;
           end if;
         end if;
    end if;
    Q <= std_logic_vector(temp) ;    -- push out new value
    end process;
 
 
end Behavioral;