FIFO_to_MGT_RAW_FSM.vhd File Reference

FSM to read RAW Event data from Link Output FIFO to MGT for process FPGA. More...

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Entities
FIFO_to_MGT_RAW_FSM	entity
	FSM to read RAW Event data from Link Output FIFO to MGT for process FPGA. More...
Behavioral	architecture
	FSM to read RAW Event data from Link Output FIFO to MGT for process FPGA. More...

Detailed Description

FSM to read RAW Event data from Link Output FIFO to MGT for process FPGA.

This FSM reads RAW frames from Link Output FIFO and writes into MGT to transmit to cFPGA. This FSM handles one full frame at a time without pausing. It monitors the RAW_frame_counter to find out if there are Frames waiting to be transmitted to cFPGA. The Frames are only transmitted when cFPGA indicates it is ready to receive data by setting ctrl_RAW_ready signal to 1. If ctrl_RAW_ready signal is set to 0 by cFPGA, this indicates cFPGA is not ready to receive data, in this case events accumulate in Link Output FIFO until occupancy reaches a pre-define prog_FULL level, at this time, Link Output FIFO stops receiving data. The data transmission of MGT is at 11.2 Gbps.

Author

Saeed Taghavi

Definition in file FIFO_to_MGT_RAW_FSM.vhd.