eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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FIFO_to_MGT_RAW_FSM.vhd
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1 
15 
16 
17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL;
19 
20 -- Uncomment the following library declaration if using
21 -- arithmetic functions with Signed or Unsigned values
22 use IEEE.NUMERIC_STD.ALL;
23 
24 library TOB_rdout_lib;
25 use TOB_rdout_lib.TOB_rdout_ip_pkg.ALL;
26 use TOB_rdout_lib.data_type_pkg.all;
27 
29 entity FIFO_to_MGT_RAW_FSM is
30  Port (
31 -- RST : in STD_LOGIC;
33  TOB_FIFO_sw_rst : in std_logic ;
34  clk_in_280M : in STD_LOGIC;
36  RAW_ready_in : in std_logic ;
38  frame_counter : in STD_LOGIC_VECTOR (11 downto 0);
40  FIFO_MGT_TOBs : in STD_LOGIC_VECTOR (32 downto 0);
42  FIFO_MGT_TOB_valid : in STD_LOGIC;
44  LO_FIFO_empty : in std_logic;
46  FIFO_MGT_rd_en : out STD_LOGIC;
48  frame_counter_dec_en : out STD_LOGIC;
50  RAW_data_out : out STD_LOGIC_VECTOR (31 downto 0);
52  RAW_data_is_char : out STD_LOGIC;
54  RAW_data_out_valid : out STD_LOGIC;
56  raw_data_mgt_fsm : out STD_LOGIC_VECTOR (7 downto 0)
57  );
58 end FIFO_to_MGT_RAW_FSM;
59 
61 architecture Behavioral of FIFO_to_MGT_RAW_FSM is
62 
63 -- CHAR constants are defined in data_type_pkg.vhd
64 -- for reference only
71 
72 --************************** Register Declarations ****************************
73  signal clk_in_280M_i : STD_LOGIC;
74 
75  signal T_TOB_out_valid_i : STD_LOGIC;
76  signal TOB_in_is_char_i : STD_LOGIC;
77  signal TOBs_in_i : STD_LOGIC_VECTOR (31 downto 0);
78  signal MGT_fifo_rd_en_i : STD_LOGIC;
79  signal TOBs_out_i, TOBs_in_tmp_1dly : STD_LOGIC_VECTOR (31 downto 0);
80  signal TOB_out_is_char_i, TOB_in_is_char_tmp_1dly : STD_LOGIC;
81 
82  signal frame_counter_dec_en_i : STD_LOGIC;
83 
84 
85  TYPE STATE_TYPE IS (
86  idle, decrement1, decrement2, rd_fifo1, rd_fifo2, tx_data_SOF1, tx_data_SOF2, tx_data1, tx_data2, tx_data_EOF1, tx_data_EOF2,
87  wait1, wait2, wait3, wait4
88  );
89 
90  SIGNAL current_state : STATE_TYPE;
91 
92 begin
93 -- input ports
94  clk_in_280M_i <= clk_in_280M ;
95 
96 -- output port
97  FIFO_MGT_rd_en <= MGT_fifo_rd_en_i ;
98 
99 
100 U1_clk_proc : process (clk_in_280M_i) -- to remove timing errors
101  begin
102  if clk_in_280M_i'event and clk_in_280M_i = '1' then
103  -- output ports
104  RAW_data_out <= TOBs_out_i; -- TOB data out to MGT
105  RAW_data_is_char <= TOB_out_is_char_i ; -- TOB data out to MGT is CHAR
106  RAW_data_out_valid <= T_TOB_out_valid_i ; -- TOB data out is valid
107  frame_counter_dec_en <= frame_counter_dec_en_i ;
108  end if;
109  end process;
110 
111 U2_clk_proc : process (clk_in_280M_i) -- to remove timing errors
112  begin
113  if clk_in_280M_i'event and clk_in_280M_i = '1' then
114  if MGT_fifo_rd_en_i = '1' then
115  TOBs_in_tmp_1dly <= FIFO_MGT_TOBs(31 downto 0); -- TOB data from FIFO
116  TOB_in_is_char_tmp_1dly <= FIFO_MGT_TOBs(32); -- TOB is char from FIFO
117  end if;
118 
119  end if;
120  end process;
121 
122 U4_rd_fsm : process (clk_in_280M_i)
123  begin
124  if clk_in_280M_i'event and clk_in_280M_i = '1' then
125  if ( TOB_FIFO_sw_rst = '1' )then -- signal is RST OR TOB_FIFO_sw_rst
126  TOBs_in_i <= (others => '0');
127  TOB_in_is_char_i <= '0';
128  current_state <= idle ;
129  else
130  TOBs_in_i <= TOBs_in_tmp_1dly; -- TOB data from FIFO
131  TOB_in_is_char_i <= TOB_in_is_char_tmp_1dly; -- TOB data from FIFO is CHAR
132  T_TOB_out_valid_i <= '0';
133  raw_data_mgt_fsm <= x"00";
134 
135  CASE current_state is
136  when idle =>
137  T_TOB_out_valid_i <= '0' ;
138  frame_counter_dec_en_i <= '0' ;
139  MGT_fifo_rd_en_i <= '0' ;
140  TOB_out_is_char_i <= '1';
141  TOBs_out_i <= X"000000" & ch_idle ; -- K28.5 idle = BC
142  raw_data_mgt_fsm <= x"01";
143  -- if no data available wait
144  if RAW_ready_in = '1' then -- if CNTL FPGA ready to receive data
145  if (frame_counter > X"000") then
146  if (LO_FIFO_empty = '1') then
147  -- if LO fifo is empty, decrement frame counter
148  frame_counter_dec_en_i <= '1' ;
149  current_state <= decrement1 ;
150  else
151  -- if LO fifo is not empty, read DATA fifos
152  current_state <= rd_fifo1 ;
153  end if;
154  end if;
155  end if;
156 
157  when decrement1 =>
158  frame_counter_dec_en_i <= '0' ;
159  current_state <= decrement2 ;
160 
161  when decrement2 =>
162  frame_counter_dec_en_i <= '0' ;
163  current_state <= idle ;
164 
165  when rd_fifo1 =>
166  T_TOB_out_valid_i <= '0' ;
167  TOB_out_is_char_i <= '1';
168  TOBs_out_i <= X"000000" & ch_idle ; -- K28.5 idle
169  raw_data_mgt_fsm <= x"02";
170  if (TOBs_in_tmp_1dly(7 downto 0) = X"7C" AND TOB_in_is_char_tmp_1dly = '1') then -- check fist data in order to save the SOF data and char
171  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
172  current_state <= tx_data_SOF1 ;
173  else
174  -- if fifo is not empty, read fifos
175  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
176  current_state <= rd_fifo1 ;
177  end if;
178 
179  when tx_data_SOF1 =>
180  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
181  TOB_out_is_char_i <= TOB_in_is_char_i;
182  TOBs_out_i <= TOBs_in_i ;
183  T_TOB_out_valid_i <= '1' ;
184  current_state <= tx_data1 ;
185  raw_data_mgt_fsm <= x"03";
186 
187  when wait1 => -- this is a FIFO rd to ensure correct SOF
188  T_TOB_out_valid_i <= '0' ;
189  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
190  TOB_out_is_char_i <= '1';
191  TOBs_out_i <= X"000000"& ch_idle ; -- K28.5 idle
192  current_state <= wait2 ; -- was
193  raw_data_mgt_fsm <= x"04";
194 
195  when wait2 => -- this is a FIFO rd to ensure correct SOF
196  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
197  TOB_out_is_char_i <= TOB_in_is_char_i;
198  TOBs_out_i <= TOBs_in_i ;
199  T_TOB_out_valid_i <= '1' ;
200  current_state <= tx_data1 ; -- was
201 
202  when tx_data1 =>
203  TOB_out_is_char_i <= TOB_in_is_char_i;
204  TOBs_out_i <= TOBs_in_i ;
205  T_TOB_out_valid_i <= '1' ;
206 
207  raw_data_mgt_fsm <= x"05";
208  if (TOBs_in_tmp_1dly(7 downto 0) = X"DC" AND TOB_in_is_char_tmp_1dly = '1') then -- check last data in order to save the SOF data and char
209  frame_counter_dec_en_i <= '1' ;
210  MGT_fifo_rd_en_i <= '0'; -- stop read data from fifos
211  current_state <= tx_data_EOF1 ;
212  else
213  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
214  -- if fifo is not empty, read fifos
215  current_state <= tx_data1 ;
216  end if;
217 
218  when tx_data_EOF1 =>
219  frame_counter_dec_en_i <= '0' ;
220  TOB_out_is_char_i <= TOB_in_is_char_i;
221  TOBs_out_i <= TOBs_in_i ;
222  T_TOB_out_valid_i <= '1' ;
223 
224  current_state <= wait3 ; -- was wait1
225  raw_data_mgt_fsm <= x"06";
226 
227  when wait3 =>
228  T_TOB_out_valid_i <= '0' ;
229  TOB_out_is_char_i <= '1';
230  TOBs_out_i <= X"000000"& ch_idle ; -- K28.5 idle
231  current_state <= tx_data_EOF2 ;
232 
233  when tx_data_EOF2 =>
234  T_TOB_out_valid_i <= '0' ;
235  TOB_out_is_char_i <= '1';
236  TOBs_out_i <= X"000000" & ch_idle ; -- K28.5 idle
237  current_state <= tx_data_EOF2 ;
238  raw_data_mgt_fsm <= x"07";
239  if RAW_ready_in = '1' then
240  if (frame_counter = X"000" ) then -- if frame_counter = X"000"
241  if (TOBs_in_i(7 downto 0) = X"DC" AND TOB_in_is_char_i = '1') then -- no new event is in FIFO (end of last event)
242  current_state <= idle ;
243  elsif LO_FIFO_empty = '1' then
244  current_state <= idle ;
245  end if;
246  else -- if frame_counter /= X"000"
247  if (TOBs_in_i(7 downto 0) = X"7C" AND TOB_in_is_char_i = '1') then -- more events are in FIFO (start of next event)
248  MGT_fifo_rd_en_i <= '1';
249  current_state <= wait1 ;
250  else
251  if (LO_FIFO_empty = '1') then
252  -- if LO fifo is empty, decrement frame counter
253  frame_counter_dec_en_i <= '1' ;
254  current_state <= decrement1 ;
255  end if;
256  end if;
257  end if;
258  end if;
259 
260  when others =>
261  NULL;
262  end case;
263  end if;
264  end if;
265  end process;
266 
267 end Behavioral;
FIFO_to_MGT_RAW_FSM.Behavioral
FSM to read RAW Event data from Link Output FIFO to MGT for process FPGA.
Definition: FIFO_to_MGT_RAW_FSM.vhd:61
FIFO_to_MGT_RAW_FSM.Behavioral.clk_in_280M_i
STD_LOGIC clk_in_280M_i
Definition: FIFO_to_MGT_RAW_FSM.vhd:73
FIFO_to_MGT_RAW_FSM
FSM to read RAW Event data from Link Output FIFO to MGT for process FPGA.
Definition: FIFO_to_MGT_RAW_FSM.vhd:29
FIFO_to_MGT_RAW_FSM.RAW_data_out
out RAW_data_out STD_LOGIC_VECTOR( 31 downto 0)
32b RAW to connect to output MGT to control FPGA
Definition: FIFO_to_MGT_RAW_FSM.vhd:50
FIFO_to_MGT_RAW_FSM.frame_counter
in frame_counter STD_LOGIC_VECTOR( 11 downto 0)
Frame counter register.
Definition: FIFO_to_MGT_RAW_FSM.vhd:38
FIFO_to_MGT_RAW_FSM.FIFO_MGT_TOBs
in FIFO_MGT_TOBs STD_LOGIC_VECTOR( 32 downto 0)
RAW from Link Output FIFO.
Definition: FIFO_to_MGT_RAW_FSM.vhd:40
FIFO_to_MGT_RAW_FSM.FIFO_MGT_rd_en
out FIFO_MGT_rd_en STD_LOGIC
Read enalbe singal to Link Output FIFO.
Definition: FIFO_to_MGT_RAW_FSM.vhd:46
FIFO_to_MGT_RAW_FSM.raw_data_mgt_fsm
out raw_data_mgt_fsm STD_LOGIC_VECTOR( 7 downto 0)
Monitor state machine status register.
Definition: FIFO_to_MGT_RAW_FSM.vhd:57
FIFO_to_MGT_RAW_FSM.LO_FIFO_empty
in LO_FIFO_empty std_logic
Link Output FIFO Empty Flag.
Definition: FIFO_to_MGT_RAW_FSM.vhd:44
FIFO_to_MGT_RAW_FSM.RAW_data_is_char
out RAW_data_is_char STD_LOGIC
RAW is CHAR to connect to output MGT to control FPGA.
Definition: FIFO_to_MGT_RAW_FSM.vhd:52
FIFO_to_MGT_RAW_FSM.RAW_data_out_valid
out RAW_data_out_valid STD_LOGIC
RAW is valid signal to wr to SPY memory.
Definition: FIFO_to_MGT_RAW_FSM.vhd:54
FIFO_to_MGT_RAW_FSM.frame_counter_dec_en
out frame_counter_dec_en STD_LOGIC
Decrement Frame Counter.
Definition: FIFO_to_MGT_RAW_FSM.vhd:48
FIFO_to_MGT_RAW_FSM.RAW_ready_in
in RAW_ready_in std_logic
Ready signal from control FPGA to receive RAW data from process FPGA.
Definition: FIFO_to_MGT_RAW_FSM.vhd:36
FIFO_to_MGT_RAW_FSM.TOB_FIFO_sw_rst
in TOB_FIFO_sw_rst std_logic
TOB Readout FIFO reset Pulse by software command ORed with SYS_RST.
Definition: FIFO_to_MGT_RAW_FSM.vhd:33
FIFO_to_MGT_RAW_FSM.FIFO_MGT_TOB_valid
in FIFO_MGT_TOB_valid STD_LOGIC
RAW from Link Output FIFO valid signal.
Definition: FIFO_to_MGT_RAW_FSM.vhd:42
TOB_rdout_ip_pkg
Definition: TOB_rdout_ip_pkg.vhd:34
data_type_pkg
Definition: data_type_pkg.vhd:34
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