Behavioral Architecture Reference

FSM to read RAW Event data from Link Output FIFO to MGT for process FPGA. More...

Processes
U1_clk_proc	( clk_in_280M_i )
U2_clk_proc	( clk_in_280M_i )
U4_rd_fsm	( clk_in_280M_i )

Types
STATE_TYPE	( idle , decrement1 , decrement2 , rd_fifo1 , rd_fifo2 , tx_data_SOF1 , tx_data_SOF2 , tx_data1 , tx_data2 , tx_data_EOF1 , tx_data_EOF2 , wait1 , wait2 , wait3 , wait4 )

Signals
clk_in_280M_i	STD_LOGIC
T_TOB_out_valid_i	STD_LOGIC
TOB_in_is_char_i	STD_LOGIC
TOBs_in_i	STD_LOGIC_VECTOR ( 31 downto 0 )
MGT_fifo_rd_en_i	STD_LOGIC
TOBs_out_i	STD_LOGIC_VECTOR ( 31 downto 0 )
TOBs_in_tmp_1dly	STD_LOGIC_VECTOR ( 31 downto 0 )
TOB_out_is_char_i	STD_LOGIC
TOB_in_is_char_tmp_1dly	STD_LOGIC
frame_counter_dec_en_i	STD_LOGIC
current_state	STATE_TYPE

Detailed Description

FSM to read RAW Event data from Link Output FIFO to MGT for process FPGA.

This FSM reads RAW frames from Link Output FIFO and writes into MGT to transmit to cFPGA. This FSM handles one full frame at a time without pausing. It monitors the RAW_frame_counter to find out if there are Frames waiting to be transmitted to cFPGA. The Frames are only transmitted when cFPGA indicates it is ready to receive data by setting ctrl_RAW_ready signal to 1. If ctrl_RAW_ready signal is set to 0 by cFPGA, this indicates cFPGA is not ready to receive data, in this case events accumulate in Link Output FIFO until occupancy reaches a pre-define prog_FULL level, at this time, Link Output FIFO stops receiving data. The data transmission of MGT is at 11.2 Gbps.

Author

Saeed Taghavi

Definition at line 61 of file FIFO_to_MGT_RAW_FSM.vhd.

Member Data Documentation

clk_in_280M_i

clk_in_280M_i STD_LOGIC

Signal

• constant ch_idle : std_logic_vector(7 downto 0) := X"BC" ; – idle char is K28.5
  • constant ch_sop1 : std_logic_vector(7 downto 0) := X"3C" ; – TOB/XTOB star of packet char is K28.1
  • constant ch_sop2 : std_logic_vector(7 downto 0) := X"7C" ; – CALO DATA start of packet char is K28.3
  • constant ch_eop : std_logic_vector(7 downto 0) := X"DC" ; – end of packet char is K28.6
  • constant slice_end : std_logic_vector(7 downto 0) := X"5C" ; – end of TOB slice char is K28.2
  • constant tx_pause : std_logic_vector(7 downto 0) := X"1C" ; – Tx Data pause is K28.0

Definition at line 73 of file FIFO_to_MGT_RAW_FSM.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/FIFO_to_MGT_RAW_FSM.vhd