eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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TOB_rdout_ip_pkg.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 05/02/2017 08:41:03 AM
6 -- Design Name:
7 -- Module Name: TOB_readout_pkg - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 
21 
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 
25 -- Uncomment the following library declaration if using
26 -- arithmetic functions with Signed or Unsigned values
27 --use IEEE.NUMERIC_STD.ALL;
28 
29 -- Uncomment the following library declaration if instantiating
30 -- any Xilinx leaf cells in this code.
31 --library UNISIM;
32 --use UNISIM.VComponents.all;
33 
34 package TOB_rdout_ip_pkg is
35 
36 
37 COMPONENT DPR_36b_1024
38  PORT (
39  clka : IN STD_LOGIC;
40  ena : IN STD_LOGIC;
41  wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
42  addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
43  dina : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
44  clkb : IN STD_LOGIC;
45  enb : IN STD_LOGIC;
46  addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
47  doutb : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
48  );
49 END COMPONENT;
50 
51 
52 COMPONENT DPR_209b_512
53  PORT (
54  clka : IN STD_LOGIC;
55  ena : IN STD_LOGIC;
56  wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
57  addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
58  dina : IN STD_LOGIC_VECTOR(208 DOWNTO 0);
59  clkb : IN STD_LOGIC;
60  enb : IN STD_LOGIC;
61  addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
62  doutb : OUT STD_LOGIC_VECTOR(208 DOWNTO 0)
63  );
64 END COMPONENT;
65 
66 
67 COMPONENT DPR_252b_512
68  PORT (
69  clka : IN STD_LOGIC;
70  ena : IN STD_LOGIC;
71  wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
72  addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
73  dina : IN STD_LOGIC_VECTOR(251 DOWNTO 0);
74  clkb : IN STD_LOGIC;
75  enb : IN STD_LOGIC;
76  addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
77  doutb : OUT STD_LOGIC_VECTOR(251 DOWNTO 0)
78  );
79 END COMPONENT;
80 
81 
82 COMPONENT FIFO_36b_512 is
83  Port (
84  clk : in STD_LOGIC;
85  srst : in STD_LOGIC;
86  din : in STD_LOGIC_VECTOR ( 35 downto 0 );
87  wr_en : in STD_LOGIC;
88  rd_en : in STD_LOGIC;
89  prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
90  prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
91  dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
92  data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
93  full : out STD_LOGIC;
94  empty : out STD_LOGIC;
95  valid : out STD_LOGIC;
96  prog_full : out STD_LOGIC
97  );
98 END COMPONENT;
99 
100 
101 COMPONENT FIFO_47b_512
102  PORT (
103  rst : IN STD_LOGIC;
104  wr_clk : IN STD_LOGIC;
105  rd_clk : IN STD_LOGIC;
106  din : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
107  wr_en : IN STD_LOGIC;
108  dout : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
109  rd_en : IN STD_LOGIC;
110  valid : OUT STD_LOGIC;
111  prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
112  prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
113  rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
114  full : OUT STD_LOGIC;
115  empty : OUT STD_LOGIC;
116  prog_full : OUT STD_LOGIC
117  );
118 END COMPONENT;
119 
120 COMPONENT FIFO_54b_512
121  PORT (
122  rst : IN STD_LOGIC;
123  wr_clk : IN STD_LOGIC;
124  rd_clk : IN STD_LOGIC;
125  din : IN STD_LOGIC_VECTOR(53 DOWNTO 0);
126  wr_en : IN STD_LOGIC;
127  rd_en : IN STD_LOGIC;
128  dout : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
129  full : OUT STD_LOGIC;
130  empty : OUT STD_LOGIC;
131  valid : OUT STD_LOGIC
132  );
133 END COMPONENT;
134 
135 
136 COMPONENT FIFO_209b_512
137  PORT (
138  clk : IN STD_LOGIC;
139  srst : IN STD_LOGIC;
140  din : IN STD_LOGIC_VECTOR(208 DOWNTO 0);
141  wr_en : IN STD_LOGIC;
142  rd_en : IN STD_LOGIC;
143  prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
144  prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
145  dout : OUT STD_LOGIC_VECTOR(208 DOWNTO 0);
146  full : OUT STD_LOGIC;
147  empty : OUT STD_LOGIC;
148  valid : OUT STD_LOGIC;
149  data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
150  prog_full : OUT STD_LOGIC
151  );
152 END COMPONENT;
153 
154 
155 COMPONENT FIFO_252b_512
156  PORT (
157  rst : IN STD_LOGIC;
158  wr_clk : IN STD_LOGIC;
159  rd_clk : IN STD_LOGIC;
160  din : IN STD_LOGIC_VECTOR(251 DOWNTO 0);
161  wr_en : IN STD_LOGIC;
162  rd_en : IN STD_LOGIC;
163  prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
164  prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
165  dout : OUT STD_LOGIC_VECTOR(251 DOWNTO 0);
166  full : OUT STD_LOGIC;
167  empty : OUT STD_LOGIC;
168  valid : OUT STD_LOGIC;
169  wr_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
170  rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
171  prog_full : OUT STD_LOGIC
172  );
173 END COMPONENT;
174 
175 
176 COMPONENT FIFO_33b_8192
177  PORT (
178  wr_clk : IN STD_LOGIC;
179  wr_rst : IN STD_LOGIC;
180  rd_clk : IN STD_LOGIC;
181  rd_rst : IN STD_LOGIC;
182  din : IN STD_LOGIC_VECTOR(32 DOWNTO 0);
183  wr_en : IN STD_LOGIC;
184  rd_en : IN STD_LOGIC;
185  prog_full_thresh_assert : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
186  prog_full_thresh_negate : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
187  dout : OUT STD_LOGIC_VECTOR(32 DOWNTO 0);
188  full : OUT STD_LOGIC;
189  empty : OUT STD_LOGIC;
190  valid : OUT STD_LOGIC;
191  rd_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
192  wr_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
193  prog_full : OUT STD_LOGIC
194  );
195 END COMPONENT;
196 
197 
198 COMPONENT ila_ipbus_fabric_rd_wr
199 PORT (
200  clk : IN STD_LOGIC;
201  probe0 : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
202  probe1 : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
203  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
204  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
205  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
206  probe5 : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
207  probe6 : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
208  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
209  probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
210  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
211 );
212 END COMPONENT ;
213 
214 
215 component clk_wiz_tst
216 port
217  (-- Clock in ports
218  -- Clock out ports
219  clk_160M : out std_logic;
220  clk_200M : out std_logic;
221  clk_280M : out std_logic;
222  -- Status and control signals
223  reset : in std_logic;
224  locked : out std_logic;
225  clk_in1 : in std_logic
226  );
227 end component;
228 
229 
230 COMPONENT ila_227_bits
231 
232 PORT (
233  clk : IN STD_LOGIC;
234  probe0 : IN STD_LOGIC_VECTOR(226 DOWNTO 0);
235  probe1 : IN STD_LOGIC_VECTOR(226 DOWNTO 0)
236 );
237 END COMPONENT ;
238 
239 
240 end TOB_rdout_ip_pkg;
241 
242 
243 
244 
245 package body TOB_rdout_ip_pkg is
246 
247 
248 
249 end TOB_rdout_ip_pkg;
TOB_rdout_ip_pkg
Definition: TOB_rdout_ip_pkg.vhd:34
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