XTOBs_sorting.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
 
library TOB_rdout_lib;
use TOB_rdout_lib.data_type_pkg.all;
use TOB_rdout_lib.TOB_rdout_ip_pkg.all;
 
library algolib;
use algolib.AlgoDataTypes.all;
 
library Infrastructure_lib;
 
entity XTOBs_sorting is
    Generic
        (
    FPGA_NUMBER : integer := 1
        ) ;
    Port (
        L1A_in            : in STD_LOGIC;
       XTOB_FIFO_sw_rst    : in std_logic ;
       XTOB_512b_in        : in AlgoXOutput;        -- array 8 x 64b words XTOBs
       XTOB_Valid_flg_in   : in STD_LOGIC_VECTOR (7 downto 0);
       XTOB_sync_in        : in STD_LOGIC;
       ALGO_XTOB_BCN_in         : in std_logic_vector(6 downto 0);
       pre_ld_wr_addr_XTOB   : in STD_LOGIC_VECTOR (8 downto 0);
       DPR_locations_to_rd   : in STD_LOGIC_VECTOR (2 downto 0);
       trigger_slice_in       : in STD_LOGIC_VECTOR(3 downto 0) ;
       FIFO_rd_en            : in STD_LOGIC;
       clk_200M_in           : in STD_LOGIC;
       clk_280M_in           : in STD_LOGIC;
       XTOB_FIFO_pFULL_THRESH_assert : in STD_LOGIC_VECTOR (8 downto 0);
       XTOB_FIFO_pFULL_THRESH_negate : in STD_LOGIC_VECTOR (8 downto 0);
       FIFO_XTOB_data_out       : out array_8_of_252b;
       XTOB_FIFO_rd_data_count     : out STD_LOGIC_VECTOR (8 downto 0);
       XTOB_FIFO_valid          : out STD_LOGIC;
       XTOB_FIFO_full           : out STD_LOGIC;
       XTOB_FIFO_empty          : out STD_LOGIC;
       XTOB_FIFO_prog_full      : out STD_LOGIC;
       xtob_data_dpram_fsm        : out STD_LOGIC_VECTOR (7 downto 0)
       );
    end XTOBs_sorting;
 
architecture RTL of XTOBs_sorting is
 
--***********************************Parameter Declarations********************
    constant DLY : time := 0 ns;
--************************** Register Declarations ****************************
 
    -- XTOB signals
    signal  TOB_valid_out_i      : array_8_of_5b;   -- TOBs valid (8 * 5b)
--    signal  SIPO_sync_vec_i      : STD_LOGIC_VECTOR (0 downto 0);
    signal  SIPO_TOB_out_i       : array_8_of_240b;  -- array 8 of XTOBs 5* 48b = 240b
    signal  XTOB_sync_out_i      : STD_LOGIC_VECTOR (7 downto 0);
 
    signal  DPR_XTOBs_in_i       : array_8_of_252b;  -- array 8 of XTOBs (48b) * 5 + 5b valid + XTOB_BCN (7b)
    signal  DPR_XTOBs_out_i      : array_8_of_252b;  -- array 8 of XTOBs (48b) * 5 + 5b valid + XTOB_BCN (7b)
    signal  FIFO_XTOB_data_out_i : array_8_of_252b;  -- array 8 of XTOBs (48b) * 5 + 5b valid + XTOB_BCN (7b)
    signal  XTOB_FIFO_wr_data_count_i : array_8_of_9b;  -- array 8 of XTOBs FIFO count (9b) * 5
    signal  XTOB_FIFO_rd_data_count_i : array_8_of_9b;  -- array 8 of XTOBs FIFO count (9b) * 5
 
    signal  DPR_XTOB_rd_addr_i     : STD_LOGIC_VECTOR (8 downto 0);
    signal  DPR_XTOB_wr_addr_i     : STD_LOGIC_VECTOR (8 downto 0);
    signal  DRP_XTOB_rd_en_i       : STD_LOGIC;
    signal  FIFO_XTOB_wr_en_i      : STD_LOGIC;
    signal  FIFO_XTOB_rd_en_i      : STD_LOGIC;
    signal  XTOB_FIFO_valid_i      : STD_LOGIC_VECTOR (7 downto 0);
    signal  XTOB_FIFO_valid_tmp    : STD_LOGIC;
    signal  XTOB_FIFO_full_i       : STD_LOGIC_VECTOR (7 downto 0);
    signal  XTOB_FIFO_full_tmp     : STD_LOGIC;
    signal  XTOB_FIFO_empty_i      : STD_LOGIC_VECTOR (7 downto 0);
    signal  XTOB_FIFO_empty_tmp    : STD_LOGIC;
    signal  XTOB_FIFO_prog_full_i  : STD_LOGIC_VECTOR (7 downto 0);
    signal  XTOB_FIFO_prog_full_tmp  : STD_LOGIC;
    signal  ALGO_XTOB_BCN_out_i    : std_logic_vector (6 downto 0); -- sorted XTOB BCN with delay through ALGO/sorting block
 
--  ####### Mark  signals  ########
--attribute mark_debug : string ;
-- attribute mark_debug of signal_name : signal is "true" ;
    attribute TIG       : string ;
    attribute TIG of XTOB_FIFO_rd_data_count_i : signal is "true" ;
 
    attribute keep       : string ;
    attribute max_fanout : integer;
    attribute keep of       XTOB_sync_in : signal is "true" ;
    attribute max_fanout of XTOB_sync_in : signal is 30;
    attribute keep of       XTOB_FIFO_prog_full_i : signal is "true" ;
    attribute max_fanout of XTOB_FIFO_prog_full_i : signal is 30;
 
    attribute keep of       XTOB_FIFO_valid_tmp : signal is "true" ;
    attribute keep of       XTOB_FIFO_full_tmp : signal is "true" ;
    attribute keep of       XTOB_FIFO_empty_tmp : signal is "true" ;
    attribute keep of       XTOB_FIFO_prog_full_tmp : signal is "true" ;
 
--   #######################################
 
begin
 
    FIFO_XTOB_rd_en_i <= FIFO_rd_en ;
 
    -- input signals
 
    XTOB_FIFO_rd_data_count <= XTOB_FIFO_rd_data_count_i(0) ;  -- generated by 280MHz
 
    XTOB_FIFO_full        <= XTOB_FIFO_full_tmp    ;
 
-- this FSM only control TOB data wr to DPRAM & FIFO
-- This state machine is responsible for reading 198-bit data (6 x 32-bit TOBs and 6 valid flags) from Circular DPRAM
-- and storing them into de-randomisation FIFO when the L1A signal is received.
-- It also controls multi-slice readout between 1 to 5 slices in sequence.
U1_TOBs_wr_FSM :  entity TOB_rdout_lib.fsm_TOB_wr_to_FIFO
    PORT map (
        CLK_IN                 => clk_200M_in ,
        TOB_FIFO_sw_rst        => XTOB_FIFO_sw_rst,    -- RST OR TOB_FIFO_sw_rst
        L1A_in                 => L1A_in ,
        -- this is sync signal which enables WR addr to increase
        -- can be either TOB_eg_sync_in or TOB_tau_sync_in as they are identical
        SIPO_sync_in           => XTOB_sync_in ,
        pre_ld_wr_addr         => pre_ld_wr_addr_XTOB ,        -- i/p
        DPR_locations_to_rd    => DPR_locations_to_rd ,   -- number of DRP locations to read 1 to 5
        trigger_slice_in       => trigger_slice_in,       -- trigger slice number (on L1A)
        DPR_rd_addr            => DPR_XTOB_rd_addr_i ,
        DPR_wr_addr            => DPR_XTOB_wr_addr_i ,
        DRP_rd_en              => DRP_XTOB_rd_en_i ,
        FIFO_wr_en             => FIFO_XTOB_wr_en_i,
        tob_data_dpram_fsm     => xtob_data_dpram_fsm
       );
 
U2_XTOB_BCN_Delay : entity Infrastructure_lib.GeneralDelay
    generic map (
      delay => 2,   --generates delay of 2 + 1 clocks
      size  => 7)
    port map (
      clk      => clk_200M_in,
      data_in  => ALGO_XTOB_BCN_in,
      data_out => ALGO_XTOB_BCN_out_i
      );
 
 
-- The GEN_XTOB_RAM loop, generates 8 copies firmware blocks within it,these are:
--     SIPO unit - to convert serial data from 5 x 48b words to a 240b parallel word with 5-bit valid flags.
--     Dual Port RAM - scrolling memory to store data on every bunch crossing
--         This is circular Dual Port RAM. It stores 325-bit words per Bunch number.
--         The Read and Write address have the correct offset in order to read the actual XTOB data
--         associated with the BCN at the time of arrival of L1A
--    Derandomisation FIFO - to store the correct data word upon receiving an L1A
--         This is Derandomisation FIFO. It stores 325-bit words per L1A, which are read out of Circular memory.
GEN_XTOB_RAM : for i in 0 to 7 GENERATE
 
    U2_XTOBs_eg :  entity TOB_rdout_lib.SIPO_unit    -- convert 5 x array of 48b XTOBs into one 240b words for Circular DPRAMs
        Port map (
            -- 48b XTOBs from 1 ALGO block - 5 in series only bits 47:0 have data, rest are ZERO
            XTOB_in           =>  XTOB_512b_in(i)(47 downto 0),
            XTOB_valid_in     =>  XTOB_Valid_flg_in(i),     -- 1B valid signal - 5 in series
            XTOB_sync_in      =>  XTOB_sync_in,             -- 1b sync in - at start of valid XTOBs
            clk_in            =>  clk_200M_in,
            XTOB_sync_out     =>  XTOB_sync_out_i(i),      -- 1b sync out - at start of valid XTOBs
            XTOB_valid_out    =>  TOB_valid_out_i(i) ,     -- TOBs valid 5b from 1 ALGO block
            XTOB_out          =>  SIPO_TOB_out_i(i)       -- XTOBs 5 * 48b = 240b out
            );
 
--        XTOBs (5*48b) + 5b valid + 7b XTOB_BCN
        DPR_XTOBs_in_i(i)      <= ALGO_XTOB_BCN_out_i & TOB_valid_out_i(i) & SIPO_TOB_out_i(i) ;
--        SIPO_sync_vec_i(0)     <= XTOB_sync_out_i ;   -- active once every 5 clks
 
    U3_XTOB_DRP : DPR_252b_512     -- XTOBs (5*48b) + 5b valid + 7b XTOB_BCN for 1 ALGO block into DPRAM
        PORT map (
            clka   => clk_200M_in  ,      -- runs at 280M but writes 1 in 7 clks
            ena    => '1'  ,      --
            wea    => stdv(XTOB_sync_out_i(i)) ,    -- was SIPO_sync_vec_i -- this is wr en using input sync sig
            addra  => DPR_XTOB_wr_addr_i    ,
            dina   => DPR_XTOBs_in_i(i)  ,     -- this is XTOBs (5*48b) + 5b valid + 7b XTOB_BCN for 1 algo block
            clkb   => clk_200M_in  ,
            enb    => DRP_XTOB_rd_en_i  ,      -- clk/rst/addr en for DPRAM port B
            addrb  => DPR_XTOB_rd_addr_i  ,
            doutb  => DPR_XTOBs_out_i(i)       -- XTOBs (5*48b) + 5b valid + 7b XTOB_BCN for 1 algo block
            );
 
    U5_XTOBs_FIFO : FIFO_252b_512     -- XXTOBs (5*48b) + 5b valid + 7b XTOB_BCN for 1 algo block into FIFO
        PORT MAP (
            rst         => XTOB_FIFO_sw_rst, -- RST OR TOB_FIFO_sw_rst
            wr_clk      => clk_200M_in,
            rd_clk      => clk_280M_in,
            din         => DPR_XTOBs_out_i(i) , --this is XTOBs (5*48b) + 5b valid + 7b XTOB_BCN for 1 algo block
            wr_en       => FIFO_XTOB_wr_en_i,
            rd_en       => FIFO_XTOB_rd_en_i,
            dout        => FIFO_XTOB_data_out_i(i)  ,   -- sorted XTOBs output of fifo XTOBs (5*48b) + 5b valid + 7b XTOB_BCN
            prog_full_thresh_assert     => XTOB_FIFO_pFULL_THRESH_assert ,
            prog_full_thresh_negate     => XTOB_FIFO_pFULL_THRESH_negate ,
            wr_data_count  => XTOB_FIFO_wr_data_count_i(i) ,             -- occupancy of XTOB FIFO, generated by 200MHz
            rd_data_count  => XTOB_FIFO_rd_data_count_i(i) ,             -- occupancy of XTOB FIFO, generated by 280MHz
            full        => XTOB_FIFO_full_i(i)      ,
            empty       => XTOB_FIFO_empty_i(i)     ,
            valid       => XTOB_FIFO_valid_i(i)     ,
            prog_full   => XTOB_FIFO_prog_full_i(i)
            );
 
    END GENERATE GEN_XTOB_RAM ;
 
 
--U2_ila_XTOB_BCN_in : ila_ipbus_fabric_rd_wr
--PORT MAP (
--  clk    =>  clk_200M_in,
--  probe0(7 downto 0)    =>  '0' & ALGO_XTOB_BCN_in(6 downto 0),       -- 36b
--  probe0(15 downto 8)   =>  '0' & ALGO_XTOB_BCN_out_i(6 downto 0) ,       -- 36b
--  probe0(24 downto 16)  =>  DPR_XTOB_wr_addr_i (8 downto 0),       -- 36b
--  probe0(33 downto 25)  =>  DPR_XTOB_rd_addr_i (8 downto 0) ,       -- 36b
--  probe0(35 downto 34)  =>  (others => '0') ,       -- 36b
--  probe1    =>  DPR_XTOBs_in_i(0)(181 downto 146),  -- 36b
--  probe2(0) =>  XTOB_sync_out_i(0) ,   -- 1b
--  probe3(0) =>  DRP_XTOB_rd_en_i ,           -- 1b
--  probe4(0) =>  FIFO_XTOB_wr_en_i ,   -- 1b
--  probe5    =>  DPR_XTOBs_out_i(0)(181 downto 146),  -- 36b
--  probe6    =>  FIFO_XTOB_data_out_i(0)(181 downto 146),        -- 36b
--  probe7(0) =>  L1A_in,             -- 1b
--  probe8(0) =>  FIFO_XTOB_rd_en_i ,       -- 1b
--    probe9(0) =>  XTOB_sync_in              -- 1b
--);
 
-- If Process FPGA 2 & 4, then assign the XTOB FIFO 6
-- If Process FPGA 1 & 3, then assign the XTOB FIFO 4
U6_gen :
    if FPGA_NUMBER = 1 generate
        XTOB_FIFO_valid_tmp       <= XTOB_FIFO_valid_i(2)   ;
        XTOB_FIFO_full_tmp        <= XTOB_FIFO_full_i(2)    ;
        XTOB_FIFO_empty_tmp       <= XTOB_FIFO_empty_i(2)   ;
        XTOB_FIFO_prog_full_tmp   <= XTOB_FIFO_prog_full_i(2) ;
 
    elsif FPGA_NUMBER = 4 generate
        XTOB_FIFO_valid_tmp       <= XTOB_FIFO_valid_i(3)   ;
        XTOB_FIFO_full_tmp        <= XTOB_FIFO_full_i(3)    ;
        XTOB_FIFO_empty_tmp       <= XTOB_FIFO_empty_i(3)   ;
        XTOB_FIFO_prog_full_tmp   <= XTOB_FIFO_prog_full_i(3) ;
 
    elsif FPGA_NUMBER = 3 generate
        XTOB_FIFO_valid_tmp       <= XTOB_FIFO_valid_i(0)   ;
        XTOB_FIFO_full_tmp        <= XTOB_FIFO_full_i(0)    ;
        XTOB_FIFO_empty_tmp       <= XTOB_FIFO_empty_i(0)   ;
        XTOB_FIFO_prog_full_tmp   <= XTOB_FIFO_prog_full_i(0) ;
 
    else generate
        XTOB_FIFO_valid_tmp       <= XTOB_FIFO_valid_i(4)   ;
        XTOB_FIFO_full_tmp        <= XTOB_FIFO_full_i(4)    ;
        XTOB_FIFO_empty_tmp       <= XTOB_FIFO_empty_i(4)   ;
        XTOB_FIFO_prog_full_tmp   <= XTOB_FIFO_prog_full_i(4) ;
    end generate U6_gen;
 
-- register output of FIFO to remove timing violations - use ALGO Block 4 to be middle of FPGA
U6_XTOB_clk280_proc : Process (clk_280M_in)
begin
    if rising_edge (clk_280M_in) then
        FIFO_XTOB_data_out    <= FIFO_XTOB_data_out_i ;
        XTOB_FIFO_valid       <= XTOB_FIFO_valid_tmp   ;
        XTOB_FIFO_empty       <= XTOB_FIFO_empty_tmp   ;
        XTOB_FIFO_prog_full   <= XTOB_FIFO_prog_full_tmp ;
    end if;
end process;
 
end RTL;