GeneralDelay.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity GeneralDelay is
  generic (delay : integer := 1;
           size  : integer := 32
           );
 
  port (
    clk      : in  std_logic;
    data_in  : in  std_logic_vector(size-1 downto 0);
    data_out : out std_logic_vector(size-1 downto 0)
    );
end GeneralDelay;
 
architecture Behavioral of GeneralDelay is
 
  type t_DelayedSignal is array (delay downto 0) of std_logic_vector(size-1 downto 0);
  signal DelayedSignal : t_DelayedSignal := (others => (others => '0'));
 
begin
 
  dalay_proc : process (clk)
  begin
    if rising_edge(clk) then
      DelayedSignal(DelayedSignal'high)            <= data_in;
      DelayedSignal(DelayedSignal'high-1 downto 0) <= DelayedSignal(DelayedSignal'high downto 1);
    end if;
  end process;
 
  data_out <= DelayedSignal(0);
end Behavioral;