Behavioral Architecture Reference

Shift register for data delay. More...

Processes
dalay_proc	( clk )

Types
t_DelayedSignal	( delay downto 0 ) std_logic_vector ( size- 1 downto 0 )

Signals
DelayedSignal	t_DelayedSignal := ( others = > ( others = > ' 0 ' ) )

Detailed Description

Shift register for data delay.

General Shift register with custom data width and delay.

Author

Francesco Gonnella

Definition at line 23 of file GeneralDelay.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd