GeneralDelay Entity Reference

Shift register for data delay. More...

Inheritance diagram for GeneralDelay:

Entities
Behavioral	architecture
	Shift register for data delay. More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Generics
delay	integer := 1
size	integer := 32

Ports
clk	in	std_logic
data_in	in	std_logic_vector ( size- 1 downto 0 )
data_out	out	std_logic_vector ( size- 1 downto 0 )

Detailed Description

Shift register for data delay.

General Shift register with custom data width and delay.

Author

Francesco Gonnella

Definition at line 10 of file GeneralDelay.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd