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eFEX firmware
1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards
|
Files | |
| file | crc_checker.vhd [code] |
| crc checker | |
| file | ctrl_playback_ram.vhd [code] |
| control State machine of playback ram | |
| file | d_type.vhd [code] |
| d_type | |
| file | data_alignment.vhd [code] |
| Data Alignment module. | |
| file | data_path_block.vhd [code] |
| Data path block. | |
| file | efex_data_formats.vhd [code] |
| eFEX data-types and functions | |
| file | efex_topo_tx.vhd [code] |
| efex topo protocol | |
| file | fibremap_block.vhd [code] |
| eFEX Fibre mapping module | |
| file | GeneralDelay.vhd [code] |
| Shift register for data delay. | |
| file | latch_enable.vhd [code] |
| latch enable | |
| file | orbit_sm.vhd [code] |
| orbit sm | |
| file | pseudo_orbit_gen.vhd [code] |
| pseudo orbit gen | |
| file | quad_bc_alignment.vhd [code] |
| quad bc alignment | |
| file | Regsync_logic.vhd [code] |
| regsynch logic | |
| file | srl16e_35.vhd [code] |
| shift register | |
| file | srl32e_226.vhd [code] |
| shift register | |
| file | synch_stg_1.vhd [code] |
| First Stage Synchronisation of process FPGA. | |
| file | tac_sm.vhd [code] |
| First Stage state machine. | |
| file | top_synch.vhd [code] |
| Top Synchronisation. | |
1.9.1