Regsync_logic.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
  entity RegSyncLogic is
    port (
      DataIn:  in  std_logic_vector(227 downto 0);
      DataOut: out std_logic_vector(227 downto 0)
   
    );
  end RegSyncLogic;
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Architecture struct of RegSyncLogic is
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-- Nothing much here....      
      
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Begin
DataOut <= DataIn;
 
  
End struct;