RegSyncLogic Entity Reference

regsynch logic More...

Inheritance diagram for RegSyncLogic:

Entities
struct	architecture
	regsynch logic More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Ports
DataIn	in	std_logic_vector ( 227 downto 0 )
		data in
DataOut	out	std_logic_vector ( 227 downto 0 )
		data out

Detailed Description

regsynch logic

it assigns the input data to the data out.

Author

Mohammed Siyad

Definition at line 13 of file Regsync_logic.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/Regsync_logic.vhd