official/Doc/data__alignment_8vhd_source.html

 library IEEE;

 use IEEE.STD_LOGIC_1164.all;

 use IEEE.NUMERIC_STD.all;


 library algolib;

 use algolib.AlgoDataTypes.all;

 library TOB_rdout_lib;

 use TOB_rdout_lib.TOB_rdout_ip_pkg.all;

 use TOB_rdout_lib.data_type_pkg.all;

 use work.synch_type.all;

 use work.EfexDataFormats.all;


 entity data_alignment is

     generic(n_channels  : natural := N_MGT;

             FPGA_NUMBER : integer);

     port(

         TTC_clk           : in  std_logic;

         clk280            : in  std_logic;

         rx_clk280         : in  std_logic_vector(n_channels - 1 downto 0);

         MGT_Commadet      : in  std_logic_vector(n_channels - 1 downto 0);

         enable_mgt        : in  std_logic_vector(n_channels - 1 downto 0);

         BC_Reg_sel        : in  std_logic_vector(255 downto 0);

         mux_sel           : in  std_logic_vector(255 downto 0);

         sel_bcn_or_bc_cnt : in  std_logic; -- selects between real data BC value and BC delay counter

         pseudo_orbit      : out std_logic;

         start             : in  std_logic;

         start_pulse_rst   : out std_logic;

         rx_resetdone      : in  std_logic_vector(n_channels - 1 downto 0);

         reset             : in  std_logic;

         DataToAlgo        : out Algoinput;

         RAW_data          : out RAW_data_227_type;

         bc_cntr_0         : out std_logic_vector(111 downto 0);

         bc_cntr_1         : out std_logic_vector(111 downto 0);

         bc_cntr_2         : out std_logic_vector(111 downto 0);

         bc_cntr_3         : out std_logic_vector(111 downto 0);

         bc_mux_cntr_0     : out std_logic_vector(111 downto 0);

         bc_mux_cntr_1     : out std_logic_vector(111 downto 0);

         bc_mux_cntr_2     : out std_logic_vector(111 downto 0);

         bc_mux_cntr_3     : out std_logic_vector(111 downto 0);

         bcn_synch         : out std_logic_vector(63 downto 0);

         crc_error_chan    : out std_logic_vector(63 downto 0);

         -- for debug

         data_readout_0    : out std_logic_vector(223 downto 0); -- for debug

         data_readout_1    : out std_logic_vector(223 downto 0); -- for debug

         data_readout_2    : out std_logic_vector(223 downto 0); -- for debug

         data_readout_3    : out std_logic_vector(223 downto 0); -- for debug

         delay_num         : out std_logic_vector(255 downto 0); -- for debug

         Reg224_latch      : out std_logic_vector(n_channels - 1 downto 0); -- for debug

         ttc_pipe          : out std_logic_vector(n_channels - 1 downto 0); -- for debug

         delay_latch       : out std_logic_vector(n_channels - 1 downto 0); -- for debug

         eFEXPosition      : in  std_logic_vector(31 downto 0);

         sel_data_in       : in  std_logic;

         ram_data          : in  ram_data_in;

         MGT_data          : in  mgt_data_in;

         align_frame       : in  std_logic_vector(n_channels - 1 downto 0);

         disperr_error     : in  std_logic_vector(n_channels - 1 downto 0);

         notable_error     : in  std_logic_vector(n_channels - 1 downto 0)

     );

 end data_alignment;


 architecture Behavioral of data_alignment is

 ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG


     signal crc_error_chan_i : std_logic_vector(63 downto 0);

     signal MGT_Commadet_tmp : std_logic_vector(63 downto 0);


     -------------------------------------


     signal data_in_int, ram_data_tmp : mgt_data_in;

     signal dataout_after_mux ,dataout_after_mux_i ,ram_data_int       : mgt_data_out;


     --signal data_out_reg224 : mgt_data_out;

     signal dataout_before_mux        : mgt_data_out;


     --signal data_in_int, data_out_int,data_out_reg224: data_path_array (n_channels-1 downto 0);


     signal sel_reg, sel_mux                  : std_logic_vector(255 downto 0);

     --signal crc_error_flag_tmp                : std_logic_vector(48 downto 0);

     signal reg1, reg2, reg3, start_pulse_280 : std_logic;


     signal temp0, temp1, temp2, start_40, pseudo_orbit_ref, pseudo_orbit_out                                  : std_logic;

     signal bcn_0, bcn_1, bcn_2, bcn_3, bc_mux_out_0, bc_mux_out_1, bc_mux_out_2, bc_mux_out_3                 : std_logic_vector(111 downto 0);

     signal bcn_tmp_0, bcn_tmp_1, bcn_tmp_2, bcn_tmp_3, bc_mux_tmp_0, bc_mux_tmp_1, bc_mux_tmp_2, bc_mux_tmp_3 : std_logic_vector(111 downto 0);

     --signal aeqb_ch0, aeqb_ch1, aeqb_ch2, aeqb_ch3, mux_aeqb_ch0, mux_aeqb_ch1, mux_aeqb_ch2, mux_aeqb_ch3     : std_logic_vector(15 downto 0);


     signal MGT_Commadet_i : std_logic_vector(n_channels - 1 downto 0);


     type crc_error_40_type is array (n_channels - 1 downto 0) of std_logic;

     signal crc_error_40_i : crc_error_40_type;


     --signal disperr_notable_error_i: disperr_notable_error;


     --  ####### Mark signals  ########

     attribute keep       : string;

     attribute max_fanout : integer;

     attribute keep of MGT_Commadet_i : signal is "true";

 --    attribute max_fanout of MGT_Commadet_i : signal is 10;

     attribute keep of bc_cntr_0 : signal is "true";

     attribute keep of bc_cntr_1 : signal is "true";

     attribute keep of bc_cntr_2 : signal is "true";

     attribute keep of bc_cntr_3 : signal is "true";

     attribute keep of bc_mux_out_0 : signal is "true";

     attribute keep of bc_mux_out_1 : signal is "true";

     attribute keep of bc_mux_out_2 : signal is "true";

     attribute keep of bc_mux_out_3 : signal is "true";

     --   #######################################


 begin


     -- for debugging

     data_readout_0 <= dataout_before_mux(16)(223 downto 0);

     data_readout_1 <= dataout_before_mux(17)(223 downto 0);

     data_readout_2 <= dataout_before_mux(18)(223 downto 0);

     data_readout_3 <= dataout_before_mux(19)(223 downto 0);

     pseudo_orbit   <= pseudo_orbit_out;


     ----------------------------------------------------------------------------------------------------

     -- bc data before the mux bits asignment

     ----------------------------------------------------------------------------------------------------

     bcn_gen : for i in 0 to (15) generate

         bcn_0(i * 7 + 6 downto 7 * i) <= MGT_to_SuperCells(dataout_before_mux(i + 3 * i)).BCID(6 downto 0);

         bcn_1(i * 7 + 6 downto 7 * i) <= MGT_to_SuperCells(dataout_before_mux(i + 1 + 3 * i)).BCID(6 downto 0);

         bcn_2(i * 7 + 6 downto 7 * i) <= MGT_to_SuperCells(dataout_before_mux(i + 2 + 3 * i)).BCID(6 downto 0);

         bcn_3(i * 7 + 6 downto 7 * i) <= MGT_to_SuperCells(dataout_before_mux(i + 3 + 3 * i)).BCID(6 downto 0);

     end generate bcn_gen;


     --------------------------------------------------------------------------------------------------

     --- Create bc alignment blocks for each mgt 64 before the mux

     --------------------------------------------------------------------------------------------------

     bc_alignment_before_mux : for i in 0 to 15 generate

         bc_align_a : entity work.quad_bc_alignment

             port map(

                 reset     => reset,

                 clk       => TTC_clk,

                 start     => start_40,  -- start pulse for the pseudo orbit state machines

                 bcn_0     => bcn_0(7 * i + 6 downto 7 * i),

                 bcn_1     => bcn_1(7 * i + 6 downto 7 * i),

                 bcn_2     => bcn_2(7 * i + 6 downto 7 * i),

                 bcn_3     => bcn_3(7 * i + 6 downto 7 * i),

                 ref_orbit => pseudo_orbit_ref, -- pseudo orbit reference signal for all channels

                 aeqb_ch0  => open,

                 aeqb_ch1  => open,

                 aeqb_ch2  => open,

                 aeqb_ch3  => open,

                 cntr_ch0  => bcn_tmp_0(7 * i + 6 downto 7 * i),

                 cntr_ch1  => bcn_tmp_1(7 * i + 6 downto 7 * i),

                 cntr_ch2  => bcn_tmp_2(7 * i + 6 downto 7 * i),

                 cntr_ch3  => bcn_tmp_3(7 * i + 6 downto 7 * i)

             );


     end generate bc_alignment_before_mux;


     bcn_before_mux : process(TTC_clk)

     begin

         if rising_edge(TTC_clk) then    -- selects between real data BC value and BC delay counter to IPBUS

             if sel_bcn_or_bc_cnt = '1' then -- send real data BC value to IPBUS

                 bc_cntr_0 <= bcn_0;

                 bc_cntr_1 <= bcn_1;

                 bc_cntr_2 <= bcn_2;

                 bc_cntr_3 <= bcn_3;

             else                        -- send out the  BC delay counter to IPBUS

                 bc_cntr_0 <= bcn_tmp_0;

                 bc_cntr_1 <= bcn_tmp_1;

                 bc_cntr_2 <= bcn_tmp_2;

                 bc_cntr_3 <= bcn_tmp_3;

             end if;

         end if;

     end process;


     ------------------------------------------------------------------------------------------------------------------

     ---  generate the reference pseudo orbit fo all the mgts, in this instance first quad mgt0 was used as reference.

     -----------------------------------------------------------------------------------------------------------------

     orbit_ref_pseudo : entity work.pseudo_orbit_gen

         port map(

             clk          => TTC_clk,

             bcn          => bcn_0(4 downto 0),

             pseudo_orbit => pseudo_orbit_ref

         );


     -----------------------------------------------------------------------------------------

     ---- bc data after the bc mux

     ----------------------------------------------------------------------------------------


     bcn_mux_gen : for i in 0 to (15) generate

         bc_mux_out_0(7 * i + 6 downto 7 * i) <= MGT_to_SuperCells(dataout_after_mux(i + 3 * i)).BCID(6 downto 0);

         bc_mux_out_1(7 * i + 6 downto 7 * i) <= MGT_to_SuperCells(dataout_after_mux(i + 1 + 3 * i)).BCID(6 downto 0);

         bc_mux_out_2(7 * i + 6 downto 7 * i) <= MGT_to_SuperCells(dataout_after_mux(i + 2 + 3 * i)).BCID(6 downto 0);

         bc_mux_out_3(7 * i + 6 downto 7 * i) <= MGT_to_SuperCells(dataout_after_mux(i + 3 + 3 * i)).BCID(6 downto 0);

     end generate bcn_mux_gen;


     --------------------------------------------------------------------------------------

     ---- Create bc alignment blocks for each mgt 64 after the mux

     ---------------------------------------------------------------------------------------

     bc_alignment_after_mux : for i in 0 to 15 generate

         bc_align_b : entity work.quad_bc_alignment

             port map(

                 reset     => reset,

                 clk       => TTC_clk,

                 start     => start_40,  -- start pulse for the pseudo orbit state machines

                 bcn_0     => bc_mux_out_0(7 * i + 6 downto 7 * i),

                 bcn_1     => bc_mux_out_1(7 * i + 6 downto 7 * i),

                 bcn_2     => bc_mux_out_2(7 * i + 6 downto 7 * i),

                 bcn_3     => bc_mux_out_3(7 * i + 6 downto 7 * i),

                 ref_orbit => pseudo_orbit_out, -- pseudo orbit reference signal for all channels

                 aeqb_ch0  => open,

                 aeqb_ch1  => open,

                 aeqb_ch2  => open,

                 aeqb_ch3  => open,

                 cntr_ch0  => bc_mux_tmp_0(7 * i + 6 downto 7 * i),

                 cntr_ch1  => bc_mux_tmp_1(7 * i + 6 downto 7 * i),

                 cntr_ch2  => bc_mux_tmp_2(7 * i + 6 downto 7 * i),

                 cntr_ch3  => bc_mux_tmp_3(7 * i + 6 downto 7 * i)

             );

     end generate bc_alignment_after_mux;


     bcn_after_mux : process(TTC_clk)

     begin

         if rising_edge(TTC_clk) then    -- selects between real data BC value and BC delay counter to IPBUS

             if sel_bcn_or_bc_cnt = '1' then -- send real data BC value to IPBUS

                 bc_mux_cntr_0 <= bc_mux_out_0;

                 bc_mux_cntr_1 <= bc_mux_out_1;

                 bc_mux_cntr_2 <= bc_mux_out_2;

                 bc_mux_cntr_3 <= bc_mux_out_3;

             else                        -- send out the  BC delay counter to IPBUS

                 bc_mux_cntr_0 <= bc_mux_tmp_0;

                 bc_mux_cntr_1 <= bc_mux_tmp_1;

                 bc_mux_cntr_2 <= bc_mux_tmp_2;

                 bc_mux_cntr_3 <= bc_mux_tmp_3;

             end if;

         end if;

     end process;


     ---------------------------------------------------------------------------------------------------------------------

     ---  Generate the reference pseudo orbit fo all the mgts,. in this instance first quad mgt0 was used as reference.

     --------------------------------------------------------------------------------------------------------------------

     orbit_ref_pseudo_b : entity work.pseudo_orbit_gen

         port map(

             clk          => TTC_clk,

             bcn          => bc_mux_out_0(4 downto 0),

             pseudo_orbit => pseudo_orbit_out

         );


     ---------------------------------------------------------

     -- Generates start pulse for the bc alignment block.

     --------------------------------------------------------

     start_pulse_40 : process(TTC_clk)

     begin

         if TTC_clk'event and TTC_clk = '1' then

             temp0    <= start;

             temp1    <= temp0;

             temp2    <= temp1;

             start_40 <= temp1 and not temp2;

         end if;

     end process;

     start_pulse_rst <= start_40;


     --------------------------------------------------------------------------------------------------------------------------

     ---- synchronisation logic block that generates n-channels of synchronisations for n_channels of MGTs

     --------------------------------------------------------------------------------------------------------------------------

     synch_gen : for i in 0 to (n_channels - 1) generate

         u0 : entity work.top_synch

             port map(

                 rx_clk280          => rx_clk280(i),

                 TTC_clk            => TTC_clk,

                 reset              => reset,

                 enable_mgt         => enable_mgt(i),

                 MGT_Commadet       => MGT_Commadet_i(i),

                 reg_sel            => sel_reg(i + 3 + 3 * i downto i + 3 * i),

                 mux_sel            => sel_mux(i + 3 + 3 * i downto i + 3 * i),

                 start              => start_pulse_280,

                 rx_resetdone       => rx_resetdone(i),

                 reg224_latch       => Reg224_latch(i),

                 delay_latch        => delay_latch(i),

                 ttc_pipe           => ttc_pipe(i),

                 delay_num          => delay_num(i + 3 + 3 * i downto i + 3 * i),

                 bcn_synch          => bcn_synch(i),

                 data_out_reg224    => dataout_before_mux(i)(223 downto 0), -- data before mux

                 disp_notable_error => dataout_after_mux_i(i)(225 downto 224), -- two bit errors

                 crc_error_out      => dataout_after_mux_i(i)(227),

                 align_frame_out    => dataout_after_mux_i(i)(226),

                 data_out           => dataout_after_mux_i(i)(223 downto 0),

                 data_in            => data_in_int(i),

                 align_frame        => align_frame(i),

                 disperr_error      => disperr_error(i),

                 notable_error      => notable_error(i),

                 crc_error_in       =>  crc_error_chan_i(i)

             );


         --- crc generation

         u1 : entity work.crc_checker

             port map(

                 clk          => rx_clk280(i),

                 reset        => reset,

                 enable_mgt   => enable_mgt(i),

                 mgt_commdet  => MGT_Commadet_i(i),

                 rxdata       => data_in_int(i),

                 crc_error    => crc_error_chan_i(i)

             );


         ram_data_int(i)   <=  ram_data(i);

         data_in_int(i)    <=  MGT_data(i);

         MGT_Commadet_i(i) <=  MGT_Commadet(i);


     end generate synch_gen;


     crc_error_chan <= crc_error_chan_i;

     sel_reg <= BC_Reg_sel;

     sel_mux <= mux_sel;


     start_pulse : process(clk280)

     begin

         if rising_edge(clk280) then

             reg1            <= start;

             reg2            <= reg1;

             reg3            <= reg2;

             start_pulse_280 <= reg2 and not reg3;

         end if;

     end process;


      dataout_after_mux <= ram_data_int when sel_data_in ='1' else dataout_after_mux_i ;


    -- MGT_Commadet_tmp(i) when sel_data_in = '1' else MGT_Commadet(i)


     -----------------------------------------------------------------------------------------

     ------------------------------------------------------------------------------------------

     fibre_map : entity work.fibremap_block

         generic map(FPGA_NUMBER => FPGA_NUMBER)

         port map(

             eFEXPosition_in => eFEXPosition,

             MGT_data_in     => dataout_after_mux,

             RAW_data_out    => RAW_data,

             DataToAlg_out   => DataToAlgo);


 -- crc_scope  : ila_0

 --PORT MAP (

 --  clk => clk280,

 --  probe0(227 downto 0) => dataout_after_mux(0)(227 downto 0),

 --  probe0(259 downto 228) => data_in_int(0),

 --  probe0(260) => crc_error_chan_i(0),

 --  probe0(261) => crc_error_40_i(0),

 --  probe0(262) => MGT_Commadet_i(0),

 --  probe0(486 downto 263)=> dataout_before_mux(0)(223 downto 0)

 --);


 end Behavioral;

AlgoDataTypes
External data-types and functions.
Definition: AlgoDataTypes.vhd:15

EfexDataFormats
eFEX data-types and functions
Definition: efex_data_formats.vhd:352

TOB_rdout_ip_pkg
Definition: TOB_rdout_ip_pkg.vhd:34

crc_checker
crc checker
Definition: crc_checker.vhd:11

crc_checker.reset
in reset std_logic
reset
Definition: crc_checker.vhd:16

crc_checker.clk
in clk std_logic
MGT rx clock.
Definition: crc_checker.vhd:14

crc_checker.mgt_commdet
in mgt_commdet std_logic
MGT commadet.
Definition: crc_checker.vhd:19

crc_checker.rxdata
in rxdata std_logic_vector( 31 downto  0)
MGT rx data.
Definition: crc_checker.vhd:21

crc_checker.crc_error
out crc_error std_logic
crc error crc error in 40MHz clock domain
Definition: crc_checker.vhd:25

data_alignment.Behavioral
Data Alignment module.
Definition: data_alignment.vhd:73

data_alignment
Data Alignment module.
Definition: data_alignment.vhd:24

data_alignment.eFEXPosition
in eFEXPosition std_logic_vector( 31 downto  0)
Geographical position of eFEX module for dynamic mapping.
Definition: data_alignment.vhd:62

data_type_pkg
Definition: data_type_pkg.vhd:34

fibremap_block
eFEX Fibre mapping module
Definition: fibremap_block.vhd:22

fibremap_block.DataToAlg_out
out DataToAlg_out Algoinput
output to algorithm block
Definition: fibremap_block.vhd:34

fibremap_block.MGT_data_in
in MGT_data_in mgt_data_out
data in from MGT
Definition: fibremap_block.vhd:29

fibremap_block.eFEXPosition_in
in eFEXPosition_in std_logic_vector( 31 downto  0)
Geographical position of eFEX module for dynamic mapping.
Definition: fibremap_block.vhd:27

fibremap_block.RAW_data_out
out RAW_data_out RAW_data_227_type
datata out to readout block
Definition: fibremap_block.vhd:31

pseudo_orbit_gen
pseudo orbit gen
Definition: pseudo_orbit_gen.vhd:13

pseudo_orbit_gen.clk
in clk std_logic
ttc clock
Definition: pseudo_orbit_gen.vhd:16

pseudo_orbit_gen.bcn
in bcn std_logic_vector( 4 downto  0)
5 lsb of the bcn kn the data
Definition: pseudo_orbit_gen.vhd:18

pseudo_orbit_gen.pseudo_orbit
out pseudo_orbit std_logic
pseudo orbit pulse generated
Definition: pseudo_orbit_gen.vhd:21

quad_bc_alignment
quad bc alignment
Definition: quad_bc_alignment.vhd:15

quad_bc_alignment.reset
in reset std_logic
reset
Definition: quad_bc_alignment.vhd:17

quad_bc_alignment.cntr_ch2
out cntr_ch2 std_logic_vector( 6 downto  0)
counter value of channel 2
Definition: quad_bc_alignment.vhd:45

quad_bc_alignment.aeqb_ch1
out aeqb_ch1 std_logic
two counter equal in channel 1
Definition: quad_bc_alignment.vhd:35

quad_bc_alignment.aeqb_ch2
out aeqb_ch2 std_logic
two counter equal in channel 2
Definition: quad_bc_alignment.vhd:37

quad_bc_alignment.bcn_2
in bcn_2 std_logic_vector( 6 downto  0)
bunch crossing number of channel 2
Definition: quad_bc_alignment.vhd:27

quad_bc_alignment.clk
in clk std_logic
TTC 40MHz clock.
Definition: quad_bc_alignment.vhd:19

quad_bc_alignment.bcn_0
in bcn_0 std_logic_vector( 6 downto  0)
bunch crossing number of channel 1
Definition: quad_bc_alignment.vhd:23

quad_bc_alignment.aeqb_ch0
out aeqb_ch0 std_logic
two counter equal in channel 0
Definition: quad_bc_alignment.vhd:33

quad_bc_alignment.aeqb_ch3
out aeqb_ch3 std_logic
two counter equal in channel 3
Definition: quad_bc_alignment.vhd:39

quad_bc_alignment.bcn_1
in bcn_1 std_logic_vector( 6 downto  0)
bunch crossing number of channel 3
Definition: quad_bc_alignment.vhd:25

quad_bc_alignment.bcn_3
in bcn_3 std_logic_vector( 6 downto  0)
bunch crossing number of channel 3
Definition: quad_bc_alignment.vhd:29

quad_bc_alignment.cntr_ch0
out cntr_ch0 std_logic_vector( 6 downto  0)
counter value of channel 0
Definition: quad_bc_alignment.vhd:41

quad_bc_alignment.start
in start std_logic
start pulse
Definition: quad_bc_alignment.vhd:21

quad_bc_alignment.cntr_ch1
out cntr_ch1 std_logic_vector( 6 downto  0)
counter value of channel 1
Definition: quad_bc_alignment.vhd:43

quad_bc_alignment.cntr_ch3
out cntr_ch3 std_logic_vector( 6 downto  0)
counter value of channel 3
Definition: quad_bc_alignment.vhd:48

quad_bc_alignment.ref_orbit
in ref_orbit std_logic
orbit reference signal
Definition: quad_bc_alignment.vhd:31

synch_type
Definition: synch_type_pkg.vhd:23

top_synch
Top Synchronisation.
Definition: top_synch.vhd:24

top_synch.rx_clk280
in rx_clk280 std_logic
rx clock of the mgt
Definition: top_synch.vhd:28

top_synch.delay_num
out delay_num std_logic_vector( 3 downto  0)
first stage dealy counter value
Definition: top_synch.vhd:52

top_synch.reset
in reset std_logic
reset active high
Definition: top_synch.vhd:32

top_synch.crc_error_out
out crc_error_out std_logic
crc_error to the error counter
Definition: top_synch.vhd:62

top_synch.rx_resetdone
in rx_resetdone std_logic
rx reset done of the MGT
Definition: top_synch.vhd:44

top_synch.MGT_Commadet
in MGT_Commadet std_logic
comma detected for incoming data
Definition: top_synch.vhd:36

top_synch.delay_latch
out delay_latch std_logic
delay latch
Definition: top_synch.vhd:48

top_synch.mux_sel
in mux_sel std_logic_vector( 3 downto  0)
setting BC mux
Definition: top_synch.vhd:40

top_synch.align_frame
in align_frame std_logic
bit indicating if data is an alignment frame or not
Definition: top_synch.vhd:66

top_synch.notable_error
in notable_error std_logic
notable channel error
Definition: top_synch.vhd:72

top_synch.disperr_error
in disperr_error std_logic
disperr channel error
Definition: top_synch.vhd:70

top_synch.data_in
in data_in std_logic_vector( 31 downto  0)
rx data in
Definition: top_synch.vhd:68

top_synch.start
in start std_logic
start pulse for the calibration to start
Definition: top_synch.vhd:42

top_synch.reg224_latch
out reg224_latch std_logic
latch enable
Definition: top_synch.vhd:46

top_synch.crc_error_in
in crc_error_in std_logic
crc channel error
Definition: top_synch.vhd:75

top_synch.enable_mgt
in enable_mgt std_logic
enable mgt rx register
Definition: top_synch.vhd:34

top_synch.disp_notable_error
out disp_notable_error std_logic_vector( 1 downto  0)
combined disperr and notable errors
Definition: top_synch.vhd:58

top_synch.ttc_pipe
out ttc_pipe std_logic
ttc pipe
Definition: top_synch.vhd:50

top_synch.data_out_reg224
out data_out_reg224 std_logic_vector( 223 downto  0) :=( others => '0')
data before mux
Definition: top_synch.vhd:56

top_synch.align_frame_out
out align_frame_out std_logic
align frame output
Definition: top_synch.vhd:60

top_synch.TTC_clk
in TTC_clk std_logic
ttc clk of 40MHz
Definition: top_synch.vhd:30

top_synch.bcn_synch
out bcn_synch std_logic
bcn synch
Definition: top_synch.vhd:54

top_synch.data_out
out data_out std_logic_vector( 223 downto  0)
data out of 224 bits
Definition: top_synch.vhd:64

top_synch.reg_sel
in reg_sel std_logic_vector( 3 downto  0)
setting the first stage mux
Definition: top_synch.vhd:38