Top Synchronisation. More...

Inheritance diagram for top_synch:

Ports
rx_clk280	in	std_logic
		rx clock of the mgt
TTC_clk	in	std_logic
		ttc clk of 40MHz
reset	in	std_logic
		reset active high
enable_mgt	in	std_logic
		enable mgt rx register
MGT_Commadet	in	std_logic
		comma detected for incoming data
reg_sel	in	std_logic_vector ( 3 downto 0 )
		setting the first stage mux
mux_sel	in	std_logic_vector ( 3 downto 0 )
		setting BC mux
start	in	std_logic
		start pulse for the calibration to start
rx_resetdone	in	std_logic
		rx reset done of the MGT
reg224_latch	out	std_logic
		latch enable
delay_latch	out	std_logic
		delay latch
ttc_pipe	out	std_logic
		ttc pipe
delay_num	out	std_logic_vector ( 3 downto 0 )
		first stage dealy counter value
bcn_synch	out	std_logic
		bcn synch
data_out_reg224	out	std_logic_vector ( 223 downto 0 ) := ( others = > ' 0 ' )
		data before mux
disp_notable_error	out	std_logic_vector ( 1 downto 0 )
		combined disperr and notable errors
align_frame_out	out	std_logic
		align frame output
crc_error_out	out	std_logic
		crc_error to the error counter
data_out	out	std_logic_vector ( 223 downto 0 )
		data out of 224 bits
align_frame	in	std_logic
		bit indicating if data is an alignment frame or not
data_in	in	std_logic_vector ( 31 downto 0 )
		rx data in
disperr_error	in	std_logic
		disperr channel error
notable_error	in	std_logic
		notable channel error
crc_error_in	in	std_logic
		crc channel error

Detailed Description

Top Synchronisation.

This synchronisation block performs following task:

It synchronises the data from the MGT(32 bits) to the 40MHz TTC (226 bits) clock domain.
Detects the Start of which is flagged by the MGT_commadet signal.
In the first stage of the synchronisation it measures the time between the arrival of MGT_commadet and the rising edge of ttc_clk and save the value to register
The second stage of the synchronisation is there to synchronise all the channels in BCN level, using pseudo orbit that are generated from 5 lsb of the BCN.
The muxs of the first and second stages are set through the IPbus
It synchronise the MGT and CRC errors with the incoming data

A simplified block diagram of top_synch

Definition at line 24 of file top_synch.vhd.

The documentation for this class was generated from the following file:

Entities