Behavioral Architecture Reference

Top Synchronisation. More...

Processes
synch_bcn	( TTC_clk )
pipe_ttc_clk	( rx_clk280 )
reg_delay_cnt	( rx_clk280 )

Signals
latch_enable	std_logic
temp0	std_logic
temp1	std_logic
Reg_enable	std_logic
commdet_delay	std_logic
delay_cnt	std_logic_vector ( 3 downto 0 )
mux_cntrl	std_logic_vector ( 3 downto 0 )
data_delay	std_logic_vector ( 3 downto 0 )
data_out_int	std_logic_vector ( 227 downto 0 )
dataout	std_logic_vector ( 227 downto 0 )
temp2	std_logic
ttc_redge	std_logic
ttc_20M	std_logic
bcn	std_logic_vector ( 4 downto 0 )
reg_sel_i	std_logic_vector ( 4 downto 0 )
data_out_int_i	std_logic_vector ( 227 downto 0 )
crc_error_i	std_logic

Instantiations
shift_register	SRLC32E_226 <Entity SRLC32E_226>
dtype	d_type <Entity d_type>
state_machine	tac_sm <Entity tac_sm>
synch_1	synch_stage_1 <Entity synch_stage_1>
latch	latch_enable <Entity latch_enable>

Detailed Description

Top Synchronisation.

This synchronisation block performs following task:

• It synchronises the data from the MGT(32 bits) to the 40MHz TTC (226 bits) clock domain.
• Detects the Start of which is flagged by the MGT_commadet signal.
• In the first stage of the synchronisation it measures the time between the arrival of MGT_commadet and the rising edge of ttc_clk and save the value to register
• The second stage of the synchronisation is there to synchronise all the channels in BCN level, using pseudo orbit that are generated from 5 lsb of the BCN.
• The muxs of the first and second stages are set through the IPbus
• It synchronise the MGT and CRC errors with the incoming data

A simplified block diagram of top_synch

Author

Mohammed Siyad

Definition at line 79 of file top_synch.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/top_synch.vhd