tac_sm Entity Reference

First Stage state machine. More...

Inheritance diagram for tac_sm:

Entities
fsm	architecture
	First Stage state machine. More...

Libraries
IEEE
xil_defaultlib

Use Clauses
STD_LOGIC_1164
std_logic_arith

Ports
clk_280M	in	std_logic
		MGT rx clock of 280MHz for process and 160MHz for control.
reset	in	std_logic
		reset
TTC_CLK_edge	in	std_logic
		raising edge of TTC clock of 40NHz
MGT_Commadet	in	std_logic
		MGT commadet.
Start	in	std_logic
		start of synchronisation
rx_resetdone	in	std_logic
Reg_enable	out	std_logic
		enable
Mux_Value	out	std_logic_vector ( 3 DOWNTO 0 )
		delay count

Detailed Description

First Stage state machine.

First stage timing auto calibration state machine. When start signal is received the state machine will start to measures the time between the arrival of MGT_commadet and the rising edge of ttc_clk. It generate delay count and send to the delay register

Author

Mohammed Siyad

Definition at line 15 of file tac_sm.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd