fsm Architecture Reference

First Stage state machine. More...

Processes
clocked_proc	( clk_280M )

Types
STATE_TYPE	( idle , wt_rstdone , wt_comma , wt_ttc_redge )

Signals
delay_count	unsigned ( 3 downto 0 )
current_state	STATE_TYPE

Detailed Description

First Stage state machine.

First stage timing auto calibration state machine. When start signal is received the state machine will start to measures the time between the arrival of MGT_commadet and the rising edge of ttc_clk. It generate delay count and send to the delay register

Author

Mohammed Siyad

Definition at line 37 of file tac_sm.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd