fibremap_block.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library algolib;
use algolib.AlgoDataTypes.all;
use work.synch_type.all;
use work.EfexDataFormats.all;
library TOB_rdout_lib;
use TOB_rdout_lib.TOB_rdout_ip_pkg.all;
use TOB_rdout_lib.data_type_pkg.all;
 
entity fibremap_block is
    generic(FPGA_NUMBER : integer);
 
    port(
        eFEXPosition_in : in  std_logic_vector(31 downto 0);
        MGT_data_in     : in  mgt_data_out;
        RAW_data_out    : out RAW_data_227_type;
        DataToAlg_out   : out Algoinput 
    );
end fibremap_block;
 
architecture struct of fibremap_block is
 
    -- The following are 3-dimensional arrays that hold the data from the MGTs,
    -- organised into eta and phi space, but still grouped into fibres.
    signal EmSyncIn     : FibreAllEm;
    signal EmSyncOut    : FibreAllEm;
    signal HadSyncIn    : FibreAllHad;
    signal HadSyncOut   : FibreAllHad;
    signal SpareSyncIn  : FibreAllSpare;
    signal SpareSyncOut : FibreAllSpare;
 
    signal fpga_number_sig : integer;
 
    ----------------------------------------------------------------------------------------------------
begin
    fpga_number_sig <= FPGA_NUMBER;
 
    -- Organise data from MGTs using this procedure:
    FibreArrayBuilder(
        fpga_number_sig,
        -- Inputs:
        MGT_data_in,
        -- Outputs:
        EmSyncIn,
        HadSyncIn,
        SpareSyncIn
    );
 
    RAW_data_out <= to_raw_data(EmSyncIn, HadSyncIn);
 
    -- Em data:
    gen_Em_eta : for x in 0 to NUM_FIB_Em_ETA - 1 generate
        gen_Em_phi : for y in 0 to NUM_FIB_Em_PHI - 1 generate
            Emsync : entity work.RegSyncLogic
                port map(DataIn => EmSyncIn(x)(y), DataOut => EmSyncOut(x)(y));
        end generate gen_Em_phi;
    end generate gen_Em_eta;
 
    -- Had data:
    gen_Had_eta : for x in 0 to NUM_FIB_Had_ETA - 1 generate
        gen_Had_phi : for y in 0 to NUM_FIB_Had_PHI - 1 generate
            Hadsync : entity work.RegSyncLogic
                port map(DataIn => HadSyncIn(x)(y), DataOut => HadSyncOut(x)(y));
        end generate gen_Had_phi;
    end generate gen_Had_eta;
 
    -- Spare data:
    gen_spare : for x in 0 to NUM_FIB_SPARE - 1 generate
        sparesync : entity work.RegSyncLogic
            port map(DataIn => SpareSyncIn(x), DataOut => SpareSyncOut(x));
    end generate gen_spare;
 
    -- Re-map output of sync logic into format expected by algorithm logic:
    DataToAlg_out <= AlgoTowerBuilder(EmSyncOut, HadSyncOut, SpareSyncOut, eFEXPosition_in);
 
end struct;