data_alignment Entity Reference

Data Alignment module. More...

Inheritance diagram for data_alignment:

Entities
Behavioral	architecture
	Data Alignment module. More...

Libraries
IEEE
algolib
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
AlgoDataTypes	Package <AlgoDataTypes>
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>
synch_type	Package <synch_type>
EfexDataFormats	Package <EfexDataFormats>

Generics
n_channels	natural := N_MGT
FPGA_NUMBER	integer

Ports
TTC_clk	in	std_logic
clk280	in	std_logic
rx_clk280	in	std_logic_vector ( n_channels- 1 downto 0 )
MGT_Commadet	in	std_logic_vector ( n_channels- 1 downto 0 )
enable_mgt	in	std_logic_vector ( n_channels- 1 downto 0 )
BC_Reg_sel	in	std_logic_vector ( 255 downto 0 )
mux_sel	in	std_logic_vector ( 255 downto 0 )
sel_bcn_or_bc_cnt	in	std_logic
pseudo_orbit	out	std_logic
start	in	std_logic
start_pulse_rst	out	std_logic
rx_resetdone	in	std_logic_vector ( n_channels- 1 downto 0 )
reset	in	std_logic
DataToAlgo	out	Algoinput
RAW_data	out	RAW_data_227_type
bc_cntr_0	out	std_logic_vector ( 111 downto 0 )
bc_cntr_1	out	std_logic_vector ( 111 downto 0 )
bc_cntr_2	out	std_logic_vector ( 111 downto 0 )
bc_cntr_3	out	std_logic_vector ( 111 downto 0 )
bc_mux_cntr_0	out	std_logic_vector ( 111 downto 0 )
bc_mux_cntr_1	out	std_logic_vector ( 111 downto 0 )
bc_mux_cntr_2	out	std_logic_vector ( 111 downto 0 )
bc_mux_cntr_3	out	std_logic_vector ( 111 downto 0 )
bcn_synch	out	std_logic_vector ( 63 downto 0 )
crc_error_chan	out	std_logic_vector ( 63 downto 0 )
data_readout_0	out	std_logic_vector ( 223 downto 0 )
data_readout_1	out	std_logic_vector ( 223 downto 0 )
data_readout_2	out	std_logic_vector ( 223 downto 0 )
data_readout_3	out	std_logic_vector ( 223 downto 0 )
delay_num	out	std_logic_vector ( 255 downto 0 )
Reg224_latch	out	std_logic_vector ( n_channels- 1 downto 0 )
ttc_pipe	out	std_logic_vector ( n_channels- 1 downto 0 )
delay_latch	out	std_logic_vector ( n_channels- 1 downto 0 )
eFEXPosition	in	std_logic_vector ( 31 downto 0 )
		Geographical position of eFEX module for dynamic mapping.
sel_data_in	in	std_logic
ram_data	in	ram_data_in
MGT_data	in	mgt_data_in
align_frame	in	std_logic_vector ( n_channels- 1 downto 0 )
disperr_error	in	std_logic_vector ( n_channels- 1 downto 0 )
notable_error	in	std_logic_vector ( n_channels- 1 downto 0 )

Detailed Description

Data Alignment module.

The Data alignment module receives data from the MGTs, synchronise them and rem.

Data alignment logic diagram

Author

Ian Brawn

Francesco Gonnella

Mohammed Siyad

Definition at line 24 of file data_alignment.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/data_alignment.vhd