Behavioral Architecture Reference

Data Alignment module. More...

Processes
bcn_before_mux	( TTC_clk )
bcn_after_mux	( TTC_clk )
start_pulse_40	( TTC_clk )
start_pulse	( clk280 )
	Pipe line for the start signal in 280m clock domain and make it as a pulse.

Types
crc_error_40_type	( n_channels- 1 downto 0 ) std_logic

Signals
crc_error_chan_i	std_logic_vector ( 63 downto 0 )
MGT_Commadet_tmp	std_logic_vector ( 63 downto 0 )
data_in_int	mgt_data_in
ram_data_tmp	mgt_data_in
dataout_after_mux	mgt_data_out
dataout_after_mux_i	mgt_data_out
ram_data_int	mgt_data_out
dataout_before_mux	mgt_data_out
sel_reg	std_logic_vector ( 255 downto 0 )
sel_mux	std_logic_vector ( 255 downto 0 )
reg1	std_logic
reg2	std_logic
reg3	std_logic
start_pulse_280	std_logic
temp0	std_logic
temp1	std_logic
temp2	std_logic
start_40	std_logic
pseudo_orbit_ref	std_logic
pseudo_orbit_out	std_logic
bcn_0	std_logic_vector ( 111 downto 0 )
bcn_1	std_logic_vector ( 111 downto 0 )
bcn_2	std_logic_vector ( 111 downto 0 )
bcn_3	std_logic_vector ( 111 downto 0 )
bc_mux_out_0	std_logic_vector ( 111 downto 0 )
bc_mux_out_1	std_logic_vector ( 111 downto 0 )
bc_mux_out_2	std_logic_vector ( 111 downto 0 )
bc_mux_out_3	std_logic_vector ( 111 downto 0 )
bcn_tmp_0	std_logic_vector ( 111 downto 0 )
bcn_tmp_1	std_logic_vector ( 111 downto 0 )
bcn_tmp_2	std_logic_vector ( 111 downto 0 )
bcn_tmp_3	std_logic_vector ( 111 downto 0 )
bc_mux_tmp_0	std_logic_vector ( 111 downto 0 )
bc_mux_tmp_1	std_logic_vector ( 111 downto 0 )
bc_mux_tmp_2	std_logic_vector ( 111 downto 0 )
bc_mux_tmp_3	std_logic_vector ( 111 downto 0 )
MGT_Commadet_i	std_logic_vector ( n_channels- 1 downto 0 )
crc_error_40_i	crc_error_40_type

Attributes
keep	string
max_fanout	integer
keep	signal is " true "

Instantiations
bc_align_a	quad_bc_alignment <Entity quad_bc_alignment>
orbit_ref_pseudo	pseudo_orbit_gen <Entity pseudo_orbit_gen>
bc_align_b	quad_bc_alignment <Entity quad_bc_alignment>
orbit_ref_pseudo_b	pseudo_orbit_gen <Entity pseudo_orbit_gen>
u0	top_synch <Entity top_synch>
	comma detected for incoming data
u1	crc_checker <Entity crc_checker>
fibre_map	fibremap_block <Entity fibremap_block>

Detailed Description

Data Alignment module.

The Data alignment module receives data from the MGTs, synchronise them and rem.

Data alignment logic diagram

Author

Ian Brawn

Francesco Gonnella

Mohammed Siyad

Definition at line 73 of file data_alignment.vhd.

Member Data Documentation

u0

u0 top_synch

Instantiation

comma detected for incoming data

not in the table error in the MGT

Definition at line 301 of file data_alignment.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/data_alignment.vhd