crc_checker.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
 entity crc_checker is
 port (
    clk         :in std_logic;
    reset        :in std_logic;
    enable_mgt   : in  std_logic;
    mgt_commdet :in std_logic;
    rxdata      :in std_logic_vector(31 downto 0);
    crc_error   :out std_logic
    );
 end crc_checker;   
 
 architecture behavioral of crc_checker is
 constant REVERSE_BIT_ORDER : boolean := TRUE;
 
 signal start_rxcrc_i : std_logic := '0';
 signal start_rxcrc_temp : std_logic := '0';
 
 signal rx_data_i     : std_logic_vector(31 downto 0);
 signal rx_crc_i      : std_logic_vector(8 downto 0) := (others => '0');
 signal rx_crc_temp   : std_logic_vector(8 downto 0) := (others => '0');
 signal enable_i      :  std_logic;     
 signal crc_error_i      :  std_logic := '0';   
 
   type state_type is (  idle, high_crc  ) ;
   signal current_state : state_type;
   signal count_40 :unsigned (2 downto 0) :=  "000";  
   
  begin
 crc_error <= crc_error_i ;
 pipe_start : process(clk)
  variable count: unsigned(2 downto 0);
         begin
            if clk' event and clk ='1' then
               if mgt_commdet ='1' or count = 6 then
                 count := (others => '0');
                 start_rxcrc_i <= '1';
               else
                 count := count + 1;
                 start_rxcrc_i <= '0';
               end if;
            end if;
         end process;
        
 -- pipeline the incoming rx data
 pipe_rxdata: process (clk)
           begin 
            if clk' event and clk ='1' then
               if mgt_commdet ='1' then
                   rx_data_i <= rxdata (31 downto 8) & x"00";
                  else
                rx_data_i <= rxdata;
            end if;
            end if;
         end process;
    
  
 RX: entity work.osum_crc9d32
    generic map(
      REVERSE_BIT_ORDER => REVERSE_BIT_ORDER)
    port map (
      d_in       => rx_data_i,
      crc_start  => start_rxcrc_i,
      clock      => clk,
      crc_out    => rx_crc_i
      );
-- check crc if is zero
  Check_crc: process (clk)
  begin
     if clk' event and clk ='1' then
            enable_i <= start_rxcrc_i;
        if (start_rxcrc_i = '1' and enable_mgt = '1' and rx_crc_i /= "000000000") then 
           crc_error_i  <= '1'; 
        else 
          crc_error_i <= '0'; 
        end if; 
        end if;
   end process;  
   
  
   
   
end behavioral;