tac_sm.vhd File Reference

First Stage state machine. More...

Go to the source code of this file.

Entities
tac_sm	entity
	First Stage state machine. More...
fsm	architecture
	First Stage state machine. More...

Detailed Description

First Stage state machine.

First stage timing auto calibration state machine. When start signal is received the state machine will start to measures the time between the arrival of MGT_commadet and the rising edge of ttc_clk. It generate delay count and send to the delay register

Author

Mohammed Siyad

Definition in file tac_sm.vhd.