eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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efex_topo_tx.vhd
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1 
14 
15 library IEEE;
16 use IEEE.STD_LOGIC_1164.ALL;
17 use IEEE.NUMERIC_STD.ALL;
18 library infrastructure_lib;
19 use infrastructure_lib.synch_type.all;
21 entity efex_topo_tx is
22 generic(
23  NCOUNTERS: integer:= 12);
24  Port (
26  clk280 :in std_logic;
28  reset : in std_logic;
30  rst :in std_logic;
32  sorted_sync :in std_logic;
34  sorted_synch_int :out std_logic;
36  bcn : in std_logic_vector(3 downto 0);
38  tob_data :in std_logic_vector(31 downto 0);
40  sorted_valid :in std_logic;
42  tx_datai_0 : out std_logic_vector( 33 downto 0);
43  tx_datai_1 : out std_logic_vector( 33 downto 0);
44  tx_datai_2 : out std_logic_vector( 33 downto 0);
45  tx_datai_3 : out std_logic_vector( 33 downto 0);
46  tx_datai_4 : out std_logic_vector( 33 downto 0);
47  tx_datai_5 : out std_logic_vector( 33 downto 0);
48  tx_datai_6 : out std_logic_vector( 33 downto 0);
49  tx_datai_7 : out std_logic_vector( 33 downto 0);
50  tx_datai_8 : out std_logic_vector( 33 downto 0);
51  tx_datai_9 : out std_logic_vector( 33 downto 0);
52  tx_datai_10 : out std_logic_vector( 33 downto 0);
53  tx_datai_11 : out std_logic_vector( 33 downto 0)
54 
55 
56 
57  );
58 end efex_topo_tx;
60 architecture Behavioral of efex_topo_tx is
61 
62 --component ila_tx
63 
64 -- port (
65 -- clk : in std_logic;
66 
67 -- probe0 : in std_logic_vector(209 downto 0)
68 
69 -- );
70 -- end component;
71 
72 signal cntr :unsigned (3 downto 0):= (others => '0');
73 signal sorted_valid_i,tx_ctrl: std_logic;
74 signal tob_data_i,tx_data_i,txdata_i,crc_data,mux_crc_data,reg_i,tob_data_reg_i: std_logic_vector(31 downto 0);
75 signal crc_start_temp,crc_error_chan : std_logic;
76 signal crc_start_i,crc_start : std_logic := '0';
77 
78 signal crc_out : std_logic_vector(8 downto 0);
79 signal mux_data_temp,mux_data,mux_data_i, tx_data,tx_data_real,tx_data_test,tx_testdata,test_data_temp: std_logic_vector(33 downto 0):= (others => '0');
80 ----------debug siganls
81 signal reg1,reg2,reset_cnt,synch_i,reset_synch:std_logic;
82 signal BCN_i,BCN_int,BCN_reg, BCN_reg_i : std_logic_vector( 3 downto 0);
83 signal probe0 :std_logic_vector(134 downto 0);
84 ------------------------------------------------
85 
86 -- ####### Tx register max fanout ########
87  attribute keep : string ;
88  attribute max_fanout : integer;
89 
90  attribute keep of tx_data : signal is "true" ;
91  attribute max_fanout of tx_data : signal is 4;
92 
93 -- #######################################
94 
95 
96 
97 begin
98 
99 tx_datai_0 <= tx_data;
100 tx_datai_1 <= tx_data;
101 tx_datai_2 <= tx_data;
102 tx_datai_3 <= tx_data;
103 tx_datai_4 <= tx_data;
104 tx_datai_5 <= tx_data;
105 tx_datai_6 <= tx_data;
106 tx_datai_7 <= tx_data;
107 tx_datai_8 <= tx_data;
108 tx_datai_9 <= tx_data;
109 tx_datai_10 <= tx_data;
110 tx_datai_11 <= tx_data;
111 
112 
113 
114  tx_data <= sorted_valid & tx_ctrl & tx_data_i;
115  -----------------------------------------------------------------------
116  --- crc generate
117  --------------------------------------------------------------------------
118 
119 
120  Latome_crc: entity infrastructure_lib.osum_crc9d32
121  generic map( REVERSE_BIT_ORDER =>true )
122  port map (
123  d_in => crc_data,
124  crc_start => crc_start,
125  clock => clk280,
126  crc_out => crc_out
127  );
128 
129 
130 
131 
132  reg_tobo_data:process(clk280,tob_data )
133 
134  begin
135  if clk280' event and clk280 ='1' then
136  reg_i <= tob_data after 1 ns ;
137  tob_data_i <= reg_i after 1 ns ;
138  tob_data_reg_i <= tob_data_i after 1 ns ;
139  sorted_valid_i <= sorted_valid after 1 ns ;
140  BCN_int <= BCN after 1 ns;
141  BCN_reg <= BCN_int after 1 ns;
142  BCN_i <= BCN_reg after 1 ns;
143 
144  BCN_reg_i <= BCN_i after 1 ns;
145 
146 
147 
148  end if;
149  end process;
150 
151 
152 
153 
154  ---------------------------------------------------------------
155  -- synch signal correction
156  -----------------------------------
157 
158  pipe_reset: process( clk280)
159 
160  begin
161 
162  if clk280' event and clk280 ='1' then
163  reg1 <= reset;
164  reg2 <= reg1;
165  end if;
166 
167 
168  end process;
169 
170  reset_synch <= reg2 and sorted_sync ;
171 
172 correction_synch: process(clk280)
173  begin
174  if clk280'event and clk280 ='1' then
175  if (reset_synch = '1') then
176  cntr <= (others=> '0');
177  synch_i <= '0';
178  else
179  if cntr = 6 then
180  cntr <= (others=> '0');
181  synch_i <= '0';
182  elsif cntr = 5 then
183  cntr <= cntr+1;
184  synch_i <= '1';
185  else
186  cntr <= cntr+1;
187  synch_i <= '0';
188  end if;
189  end if;
190  end if;
191  end process;
192 
193 
194 
195  efex_topo_sm: entity work.efex_topo_frame_sm
196  port map (
197  bcn => BCN_reg_i , --bcn_i,
198  clk => clk280,
199  reset => reset_synch,
200  crc => crc_out,
201  tobo_data => tob_data, --reg_i , --tob_data,
202  tobo_data_reg => tob_data_i,
203  tobo_sync => sorted_sync,
204  tobo_valid => sorted_valid,
205  tx_ctrl => tx_ctrl,
206  crc_start => crc_start,
207  crc_data => crc_data,
208  tx_data => tx_data_i
209 
210 
211  );
212 
213  sorted_synch_int <= synch_i;
214 
215 -- scope : ila_tx
216 -- port map (
217 -- clk => clk280,
218 -- probe0(31 downto 0) => tx_data_i,
219 -- probe0(63 downto 32) => tob_data,
220 -- probe0(64) => tx_ctrl,
221 -- probe0(65) => sorted_sync,
222 -- probe0 (66) => sorted_valid,
223 -- probe0 (70 downto 67) => bcn_i,
224 -- probe0(102 downto 71) => crc_data,
225 -- probe0(103) => crc_start,
226 -- probe0(112 downto 104) => crc_out ,
227 -- probe0( 145 downto 113) =>'0' & reg_i,
228 -- probe0( 177 downto 146) =>tob_data_reg_i,
229 -- probe0( 209 downto 178) => tob_data_i
230 
231 -- );
232 
233 
234 end Behavioral;
efex_topo_frame_sm
Definition: efex_topo_frame_sm.vhd:13
efex_topo_frame_sm.bcn
in bcn std_logic_vector( 3 DOWNTO 0)
bnc of the tobs
Definition: efex_topo_frame_sm.vhd:16
efex_topo_frame_sm.tobo_data
in tobo_data std_logic_vector( 31 DOWNTO 0)
tob data
Definition: efex_topo_frame_sm.vhd:26
efex_topo_frame_sm.reset
in reset std_logic
reset synch
Definition: efex_topo_frame_sm.vhd:24
efex_topo_frame_sm.tx_ctrl
out tx_ctrl std_logic
tx control of the MGT
Definition: efex_topo_frame_sm.vhd:36
efex_topo_frame_sm.crc
in crc std_logic_vector( 8 DOWNTO 0)
crc bits
Definition: efex_topo_frame_sm.vhd:22
efex_topo_frame_sm.clk
in clk std_logic
fabric clock of 280MHz
Definition: efex_topo_frame_sm.vhd:18
efex_topo_frame_sm.tobo_data_reg
in tobo_data_reg std_logic_vector( 31 DOWNTO 0)
tob data pipe
Definition: efex_topo_frame_sm.vhd:28
efex_topo_frame_sm.tobo_valid
in tobo_valid std_logic
tob valid
Definition: efex_topo_frame_sm.vhd:32
efex_topo_frame_sm.crc_data
out crc_data std_logic_vector( 31 DOWNTO 0)
input to the crc calculator
Definition: efex_topo_frame_sm.vhd:34
efex_topo_frame_sm.crc_start
out crc_start std_logic
stsrt crc generation
Definition: efex_topo_frame_sm.vhd:20
efex_topo_frame_sm.tx_data
out tx_data std_logic_vector( 31 DOWNTO 0)
MGT tx data.
Definition: efex_topo_frame_sm.vhd:40
efex_topo_frame_sm.tobo_sync
in tobo_sync std_logic
tob synch
Definition: efex_topo_frame_sm.vhd:30
efex_topo_tx.Behavioral
efex topo protocol
Definition: efex_topo_tx.vhd:60
efex_topo_tx
efex topo protocol
Definition: efex_topo_tx.vhd:21
efex_topo_tx.reset
in reset std_logic
reset
Definition: efex_topo_tx.vhd:28
efex_topo_tx.sorted_valid
in sorted_valid std_logic
Output data valid, high when correspondent output data are valid.
Definition: efex_topo_tx.vhd:40
efex_topo_tx.sorted_sync
in sorted_sync std_logic
Output sync, high on the first clock cycle of the BC.
Definition: efex_topo_tx.vhd:32
efex_topo_tx.tx_datai_0
out tx_datai_0 std_logic_vector( 33 downto 0)
Output data to the mgt that transimits to the L1Topo.
Definition: efex_topo_tx.vhd:42
efex_topo_tx.clk280
in clk280 std_logic
clock 280MHz
Definition: efex_topo_tx.vhd:26
efex_topo_tx.NCOUNTERS
NCOUNTERS integer := 12
number of tx mgts
Definition: efex_topo_tx.vhd:23
efex_topo_tx.bcn
in bcn std_logic_vector( 3 downto 0)
bcn from algo block
Definition: efex_topo_tx.vhd:36
efex_topo_tx.tob_data
in tob_data std_logic_vector( 31 downto 0)
Algorithm external data structure, defined in AlgoDataTypes.vhd.
Definition: efex_topo_tx.vhd:38
efex_topo_tx.sorted_synch_int
out sorted_synch_int std_logic
internally generated out put synch
Definition: efex_topo_tx.vhd:34
efex_topo_tx.rst
in rst std_logic
input reset generated by the not locked 40MHz MMC
Definition: efex_topo_tx.vhd:30
osum_crc9d32
Definition: osum_crc9d32.vhd:7
synch_type
Definition: synch_type_pkg.vhd:23
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