eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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efex_topo_tx Entity Reference

efex topo protocol More...

Inheritance diagram for efex_topo_tx:
osum_crc9d32 efex_topo_frame_sm top_efex_processor

Entities

Behavioral  architecture
 efex topo protocol More...
 

Libraries

IEEE 
infrastructure_lib 

Use Clauses

STD_LOGIC_1164 
NUMERIC_STD 
synch_type  Package <synch_type>

Generics

NCOUNTERS  integer := 12
 number of tx mgts

Ports

clk280   in   std_logic
  clock 280MHz
reset   in   std_logic
  reset
rst   in   std_logic
  input reset generated by the not locked 40MHz MMC
sorted_sync   in   std_logic
  Output sync, high on the first clock cycle of the BC.
sorted_synch_int   out   std_logic
  internally generated out put synch
bcn   in   std_logic_vector ( 3 downto 0 )
  bcn from algo block
tob_data   in   std_logic_vector ( 31 downto 0 )
  Algorithm external data structure, defined in AlgoDataTypes.vhd.
sorted_valid   in   std_logic
  Output data valid, high when correspondent output data are valid.
tx_datai_0   out   std_logic_vector ( 33 downto 0 )
  Output data to the mgt that transimits to the L1Topo.
tx_datai_1   out   std_logic_vector ( 33 downto 0 )
tx_datai_2   out   std_logic_vector ( 33 downto 0 )
tx_datai_3   out   std_logic_vector ( 33 downto 0 )
tx_datai_4   out   std_logic_vector ( 33 downto 0 )
tx_datai_5   out   std_logic_vector ( 33 downto 0 )
tx_datai_6   out   std_logic_vector ( 33 downto 0 )
tx_datai_7   out   std_logic_vector ( 33 downto 0 )
tx_datai_8   out   std_logic_vector ( 33 downto 0 )
tx_datai_9   out   std_logic_vector ( 33 downto 0 )
tx_datai_10   out   std_logic_vector ( 33 downto 0 )
tx_datai_11   out   std_logic_vector ( 33 downto 0 )

Detailed Description

efex topo protocol

This module recives Tob data,sorted synch,valid and BCN from the merging block of the Tobs. Each of which contains all of the TOBs for a Bunch Crossing (for that fibre), plus a trailer. It generates frames from eFEX tobs and sends to L1Topo. Each frame takes 1 LHC tick to be transmitted ( as the frame contains six 32 bits of data payload and last 32 bit for trailer). The bits in the unused part of the frame are all set to zero. The CRC is calculated over the full frame of 7 x 32-bit words, in this calculation the CRC field is masked by zeros and the K characters. The design inserts the CRC result into the designated trailer field before transmission.

protocol between eFEX and L1topo Diagram


Author
Mohammed Siyad

Definition at line 21 of file efex_topo_tx.vhd.


The documentation for this class was generated from the following file: