Behavioral Architecture Reference

efex topo protocol More...

Processes
reg_tobo_data	( clk280 , tob_data )
pipe_reset	( clk280 )
correction_synch	( clk280 )

Signals
cntr	unsigned ( 3 downto 0 ) := ( others = > ' 0 ' )
sorted_valid_i	std_logic
tx_ctrl	std_logic
tob_data_i	std_logic_vector ( 31 downto 0 )
tx_data_i	std_logic_vector ( 31 downto 0 )
txdata_i	std_logic_vector ( 31 downto 0 )
crc_data	std_logic_vector ( 31 downto 0 )
mux_crc_data	std_logic_vector ( 31 downto 0 )
reg_i	std_logic_vector ( 31 downto 0 )
tob_data_reg_i	std_logic_vector ( 31 downto 0 )
crc_start_temp	std_logic
crc_error_chan	std_logic
crc_start_i	std_logic := ' 0 '
crc_start	std_logic := ' 0 '
crc_out	std_logic_vector ( 8 downto 0 )
mux_data_temp	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
mux_data	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
mux_data_i	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
tx_data	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
tx_data_real	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
tx_data_test	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
tx_testdata	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
test_data_temp	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
reg1	std_logic
reg2	std_logic
reset_cnt	std_logic
synch_i	std_logic
reset_synch	std_logic
BCN_i	std_logic_vector ( 3 downto 0 )
BCN_int	std_logic_vector ( 3 downto 0 )
BCN_reg	std_logic_vector ( 3 downto 0 )
BCN_reg_i	std_logic_vector ( 3 downto 0 )
probe0	std_logic_vector ( 134 downto 0 )

Attributes
keep	string
max_fanout	integer
keep	signal is " true "
max_fanout	signal is 4

Instantiations
latome_crc	osum_crc9d32 <Entity osum_crc9d32>
efex_topo_sm	efex_topo_frame_sm <Entity efex_topo_frame_sm>

Detailed Description

efex topo protocol

This module recives Tob data,sorted synch,valid and BCN from the merging block of the Tobs. Each of which contains all of the TOBs for a Bunch Crossing (for that fibre), plus a trailer. It generates frames from eFEX tobs and sends to L1Topo. Each frame takes 1 LHC tick to be transmitted ( as the frame contains six 32 bits of data payload and last 32 bit for trailer). The bits in the unused part of the frame are all set to zero. The CRC is calculated over the full frame of 7 x 32-bit words, in this calculation the CRC field is masked by zeros and the K characters. The design inserts the CRC result into the designated trailer field before transmission.

protocol between eFEX and L1topo Diagram

Author

Mohammed Siyad

Definition at line 60 of file efex_topo_tx.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/efex_topo_tx.vhd