efex_topo_frame_sm Entity Reference

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Inheritance diagram for efex_topo_frame_sm:

Entities
fsm	architecture

Libraries
ieee
	efex_topo protocol state machine

Use Clauses
std_logic_1164
std_logic_arith

Ports
bcn	in	std_logic_vector ( 3 DOWNTO 0 )
		bnc of the tobs
clk	in	std_logic
		fabric clock of 280MHz
crc_start	out	std_logic
		stsrt crc generation
crc	in	std_logic_vector ( 8 DOWNTO 0 )
		crc bits
reset	in	std_logic
		reset synch
tobo_data	in	std_logic_vector ( 31 DOWNTO 0 )
		tob data
tobo_data_reg	in	std_logic_vector ( 31 DOWNTO 0 )
		tob data pipe
tobo_sync	in	std_logic
		tob synch
tobo_valid	in	std_logic
		tob valid
crc_data	out	std_logic_vector ( 31 DOWNTO 0 )
		input to the crc calculator
tx_ctrl	out	std_logic
		tx control of the MGT
tx_data	out	std_logic_vector ( 31 DOWNTO 0 )
		MGT tx data.

Detailed Description

Definition at line 13 of file efex_topo_frame_sm.vhd.

Member Data Documentation

ieee

ieee

Library

efex_topo protocol state machine

This module implements state machine that controls the frame of the protocol. The state machine controls the timing of the protocol between the eFEX and L1topo. It creates frame wth Tobs and trialer with calculated crc. It also generates empty frame with crc and trialer if there is no tob in that BCN.

Author

Mohammed Siyad

Definition at line 9 of file efex_topo_frame_sm.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/efex_topo_frame_sm.vhd