data_path_block.vhd File Reference

Data path block. More...

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Entities
data_path_block	entity
	Data path block. More...
Behavioral	architecture
	Data path block. More...

Detailed Description

Data path block.

The data path module is a container for three functional modules: data alignment, algorithm, local TOB sorting. This is a block diagram of the data path block:

Data path block logic diagram

The data coming form the MGTs is provided to the alignment block that decodes them to the algorithm input format.

This decoding is done differently for FPGA U1, U2, U3, U4 depending on the generic FPGA_NUMBER. Data decoding also depends on the eFEX module position that can be set at runtime with an IPbus register called "position" in the algorithm module. The value of this register is fed back from the algorithm to the data alignment module.

XTOBs coming out of the algorithm @200MHz together with the BC number are sent to output ports to be fed to the XTOB readout. Unsorted local TOBs (max 40) are sent from the algorithm to the sorting module.

Sorted tobs (max 7), coming out of the sorting module @280 MHz are sent out of the data path block. These can go either to the merging FPGAs or to the merging module. This block doesn't add any latency and does not contain any process.

Author

Ian Brawn

Francesco Gonnella

Definition in file data_path_block.vhd.