data_path_block Entity Reference

Data path block. More...

Inheritance diagram for data_path_block:

Entities
Behavioral	architecture
	Data path block. More...

Libraries
IEEE
infrastructure_lib
algolib
ipbus_lib
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
all
AlgoDataTypes	Package <AlgoDataTypes>
DataTypes	Package <DataTypes>
ipbus
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>
synch_type	Package <synch_type>
EfexDataFormats	Package <EfexDataFormats>
mgt_type	Package <mgt_type>

Generics
n_channels	natural := N_MGT
ENCODING_MODE	integer
ENABLE_INPUT_RAM	boolean
EFEX_POSITION	integer := 0
ENABLE_OUTPUT_RAMS	boolean
ENABLE_SORTING_INPUT_RAM	boolean
ENABLE_SORTING_OUTPUT_RAM	boolean
FPGA_NUMBER	integer
EG_ALGO_VERSION	std_logic_vector ( 1 downto 0 )
TAU_ALGO_VERSION	std_logic_vector ( 1 downto 0 )

Ports
clk200	in	std_logic
rx_clk280	in	std_logic_vector ( n_channels- 1 downto 0 )
		MGT clocks.
clk280	in	std_logic
		Used in the output stage of the algorithm.
reset	in	std_logic
		syncronous reset used in data_alignment
ttc_clk	in	std_logic
		40 MHz clk
in_load	in	std_logic
		clk 40MHz, 20% duty cycle
ipb_clk	in	std_logic
		ipbus clock
ipb_rst	in	std_logic
		ipbus reset
ipb_in_algo	in	ipb_wbus
		ipbus connection for algorithm
ipb_out_algo	out	ipb_rbus
		ipbus connection for algorithm
ipb_in_sorting	in	ipb_wbus
		ipbus connection for local TOB sorting
ipb_out_sorting	out	ipb_rbus
		ipbus connection for local TOB sorting
BCR_in	in	std_logic
ttc_orbit_length_reg	in	std_logic_vector ( 11 downto 0 )
bcmuxvalue_sych_reg	in	std_logic_vector ( 11 downto 0 )
sel_bcn_or_bc_cnt	in	std_logic
		selects between real data BC value (1) and BC delay counter (0) to ipbus
pseudo_orbit	out	std_logic
		Pulse generated when 5-bit BCN is 00000.
BC_Reg_sel	in	std_logic_vector ( 255 downto 0 )
		16-b BC MUX select for 16 Quads
mux_sel	in	std_logic_vector ( 255 downto 0 )
		16-b 1st stage MUX select for 16 Quads
enable_mgt	in	std_logic_vector ( n_channels- 1 downto 0 )
		MGT enable.
rx_resetdone	in	std_logic_vector ( n_channels- 1 downto 0 )
		reset done from GMTs
start_pulse_rst	out	std_logic
bc_cntr_0	out	std_logic_vector ( 111 downto 0 )
bc_cntr_1	out	std_logic_vector ( 111 downto 0 )
bc_cntr_2	out	std_logic_vector ( 111 downto 0 )
bc_cntr_3	out	std_logic_vector ( 111 downto 0 )
bc_mux_cntr_0	out	std_logic_vector ( 111 downto 0 )
bc_mux_cntr_1	out	std_logic_vector ( 111 downto 0 )
bc_mux_cntr_2	out	std_logic_vector ( 111 downto 0 )
bc_mux_cntr_3	out	std_logic_vector ( 111 downto 0 )
bcn_synch	out	std_logic_vector ( 63 downto 0 )
crc_error_chan	out	std_logic_vector ( 63 downto 0 )
RAW_data	out	RAW_data_227_type
		RAW data to Readout.
OUT_eg_Valid	out	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
		Valid signal for eg XTOBS @200MHz.
OUT_eg_Sync	out	std_logic
		Sync signal for XTOBS @200MHz marking the first XTOB of 5.
OUT_eg_XTOB	out	AlgoXOutput
		eg XTOBS 8 x 64bit @200MHz
OUT_tau_Valid	out	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
		Valid signal for eg XTOBS @200MHz.
OUT_tau_Sync	out	std_logic
		Sync signal for XTOBS @200MHz marking the first XTOB of 5.
OUT_tau_XTOB	out	AlgoXOutput
		tau XTOBS 8 x 64bit @200MHz
OUT_XTOB_BCN	out	std_logic_vector ( 11 downto 0 )
		XTOB BCN @200 MHZ referring to 5 TOBS in the BC.
OUT_sorted_eg_TOB	out	AlgoTriggerObject
		Sorted eg TOB 32bit.
OUT_sorted_eg_Sync	out	std_logic
		Sorted TOB synch @280 marking first TOB of 7.
OUT_sorted_eg_Valid	out	std_logic
		Sorted TOB valid @280.
OUT_sorted_tau_TOB	out	AlgoTriggerObject
		Sorted eg TOB 32bit.
OUT_sorted_tau_Sync	out	std_logic
		Sorted TOB synch @280 marking first TOB of 7.
OUT_sorted_tau_Valid	out	std_logic
		Sorted TOB valid @280.
OUT_TOB_BCN	out	std_logic_vector ( 11 downto 0 )
		BCN @280 MHZ referring to 7 TOBS in the BC.
delay_latch	out	std_logic_vector ( n_channels- 1 downto 0 )
delay_num	out	std_logic_vector ( 255 downto 0 )
Reg224_latch	out	std_logic_vector ( n_channels- 1 downto 0 )
ttc_pipe	out	std_logic_vector ( n_channels- 1 downto 0 )
data_readout_0	out	std_logic_vector ( 223 downto 0 )
data_readout_1	out	std_logic_vector ( 223 downto 0 )
data_readout_2	out	std_logic_vector ( 223 downto 0 )
data_readout_3	out	std_logic_vector ( 223 downto 0 )
start	in	std_logic
sel_data_in	in	std_logic
ram_data_mgt0	in	std_logic_vector ( 3647 downto 0 )
ram_data_mgt1	in	std_logic_vector ( 3647 downto 0 )
ram_data_mgt2	in	std_logic_vector ( 3647 downto 0 )
ram_data_mgt3	in	std_logic_vector ( 3647 downto 0 )
MGT_Commadet	in	std_logic_vector ( n_channels- 1 downto 0 )
MGT_Data	in	mgt_rxdata_array ( 15 downto 0 )
align_frame	in	std_logic_vector ( n_channels- 1 downto 0 )
disperr_error	in	std_logic_vector ( n_channels- 1 downto 0 )
notable_error	in	std_logic_vector ( n_channels- 1 downto 0 )

Detailed Description

Data path block.

The data path module is a container for three functional modules: data alignment, algorithm, local TOB sorting. This is a block diagram of the data path block:

Data path block logic diagram

The data coming form the MGTs is provided to the alignment block that decodes them to the algorithm input format.

This decoding is done differently for FPGA U1, U2, U3, U4 depending on the generic FPGA_NUMBER. Data decoding also depends on the eFEX module position that can be set at runtime with an IPbus register called "position" in the algorithm module. The value of this register is fed back from the algorithm to the data alignment module.

XTOBs coming out of the algorithm @200MHz together with the BC number are sent to output ports to be fed to the XTOB readout. Unsorted local TOBs (max 40) are sent from the algorithm to the sorting module.

Sorted tobs (max 7), coming out of the sorting module @280 MHz are sent out of the data path block. These can go either to the merging FPGAs or to the merging module. This block doesn't add any latency and does not contain any process.

Author

Ian Brawn

Francesco Gonnella

Definition at line 45 of file data_path_block.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/data_path_block.vhd