official/Doc/data__path__block_8vhd_source.html

 library IEEE;

 use IEEE.STD_LOGIC_1164.all;

 use IEEE.NUMERIC_STD.all;

 library infrastructure_lib;

 use infrastructure_lib.all;


 library algolib;

 use algolib.AlgoDataTypes.all;

 use algolib.DataTypes.all;


 library ipbus_lib;

 use ipbus_lib.ipbus.all;

 library TOB_rdout_lib;

 use TOB_rdout_lib.TOB_rdout_ip_pkg.all;

 use TOB_rdout_lib.data_type_pkg.all;


 use work.synch_type.all;

 use work.EfexDataFormats.all;

 use work.mgt_type.all;


 library TOB_rdout_lib;

 use TOB_rdout_lib.TOB_rdout_ip_pkg.all;


 entity data_path_block is

   generic(n_channels          : natural := N_MGT;

           ENCODING_MODE       : integer;

           ENABLE_INPUT_RAM    : boolean;

           EFEX_POSITION       : integer := 0;

           ENABLE_OUTPUT_RAMS  : boolean;

           ENABLE_SORTING_INPUT_RAM : boolean;

           ENABLE_SORTING_OUTPUT_RAM : boolean;

           FPGA_NUMBER         : integer;

           EG_ALGO_VERSION     : std_logic_vector(1 downto 0);

           TAU_ALGO_VERSION     : std_logic_vector(1 downto 0));

   port (

     clk200          : in  std_logic;

     rx_clk280       : in  std_logic_vector(n_channels-1 downto 0);

     clk280          : in  std_logic;

     reset           : in  std_logic;

     ttc_clk         : in  std_logic;

     in_load         : in  std_logic;

     --IPBus connection

     ipb_clk         : in  std_logic;

     ipb_rst         : in  std_logic;

     ipb_in_algo     : in  ipb_wbus;

     ipb_out_algo    : out ipb_rbus;

     ipb_in_sorting  : in  ipb_wbus;

     ipb_out_sorting : out ipb_rbus;

     BCR_in          : in std_logic;

     ttc_orbit_length_reg : in std_logic_vector(11 downto 0);

     bcmuxvalue_sych_reg  : in std_logic_vector(11 downto 0);

     sel_bcn_or_bc_cnt : in  std_logic;

     pseudo_orbit      : out std_logic;

     BC_Reg_sel        : in  std_logic_vector(255 downto 0);

     mux_sel           : in  std_logic_vector(255 downto 0);

     enable_mgt        : in  std_logic_vector(n_channels -1 downto 0);

     rx_resetdone      : in  std_logic_vector(n_channels -1 downto 0);

     start_pulse_rst : out std_logic;

     bc_cntr_0       : out std_logic_vector(111 downto 0);

     bc_cntr_1       : out std_logic_vector(111 downto 0);

     bc_cntr_2       : out std_logic_vector(111 downto 0);

     bc_cntr_3       : out std_logic_vector(111 downto 0);

     bc_mux_cntr_0   : out std_logic_vector(111 downto 0);

     bc_mux_cntr_1   : out std_logic_vector(111 downto 0);

     bc_mux_cntr_2   : out std_logic_vector(111 downto 0);

     bc_mux_cntr_3   : out std_logic_vector(111 downto 0);

     bcn_synch       : out std_logic_vector(63 downto 0);

     crc_error_chan  : out std_logic_vector(63 downto 0);


     RAW_data : out RAW_data_227_type;


     -- XTOBS

     OUT_eg_Valid : out std_logic_vector(OUTPUT_TOBS-1 downto 0);

     OUT_eg_Sync  : out std_logic;

     OUT_eg_XTOB  : out AlgoXOutput;


     OUT_tau_Valid : out std_logic_vector(OUTPUT_TOBS-1 downto 0);

     OUT_tau_Sync  : out std_logic;

     OUT_tau_XTOB  : out AlgoXOutput;


     OUT_XTOB_BCN : out std_logic_vector(11 downto 0);


     --- sorted TOBs

     OUT_sorted_eg_TOB   : out AlgoTriggerObject;

     OUT_sorted_eg_Sync  : out std_logic;

     OUT_sorted_eg_Valid : out std_logic;


     OUT_sorted_tau_TOB   : out AlgoTriggerObject;

     OUT_sorted_tau_Sync  : out std_logic;

     OUT_sorted_tau_Valid : out std_logic;

     OUT_TOB_BCN         : out std_logic_vector(11 downto 0);


     --- debug signals for synch

     delay_latch    : out std_logic_vector(n_channels-1 downto 0);  -- for debuging

     delay_num      : out std_logic_vector(255 downto 0);           -- for debuging

     Reg224_latch   : out std_logic_vector(n_channels-1 downto 0);  -- for debuging

     ttc_pipe       : out std_logic_vector(n_channels-1 downto 0);  -- for debuging

     data_readout_0 : out std_logic_vector(223 downto 0);

     data_readout_1 : out std_logic_vector(223 downto 0);

     data_readout_2 : out std_logic_vector(223 downto 0);

     data_readout_3 : out std_logic_vector(223 downto 0);

     start          : in  std_logic;

     --playback

      sel_data_in   : in  std_logic;

     ram_data_mgt0  : in  std_logic_vector (3647 downto 0);

     ram_data_mgt1  : in  std_logic_vector (3647 downto 0);

     ram_data_mgt2  : in  std_logic_vector (3647 downto 0);

     ram_data_mgt3  : in  std_logic_vector (3647 downto 0);

     -- MGT signals

     MGT_Commadet   : in  std_logic_vector(n_channels-1 downto 0);

     MGT_Data       : in  mgt_rxdata_array (15 downto 0);


     -- error_handling

     align_frame   : in std_logic_vector(n_channels-1 downto 0);

     disperr_error : in std_logic_vector(n_channels-1 downto 0);

     notable_error : in std_logic_vector(n_channels-1 downto 0)

     );


 end data_path_block;


 architecture Behavioral of data_path_block is


   COMPONENT ila_inputRam


 PORT (

     clk : IN STD_LOGIC;


     probe0 : IN STD_LOGIC_VECTOR(19 DOWNTO 0)

 );

 END COMPONENT  ;


   signal algo_in : AlgoInput;


   signal eg_Sync, eg_XSync : std_logic;

   signal tau_XSync         : std_logic;

   signal eg_XValid         : std_logic_vector(OUTPUT_TOBS-1 downto 0);

   signal tau_XValid        : std_logic_vector(OUTPUT_TOBS-1 downto 0);


   signal eg_TOB  : AlgoOutput;

   signal tau_TOB : AlgoOutput;


   signal eg_XTOB      : AlgoXOutput;

   signal tau_XTOB     : AlgoXOutput;

   signal eFEXPosition : std_logic_vector(31 downto 0);


   signal mgt_data_int : mgt_data_in;

   signal ram_data_int : ram_data_in;

   signal sorted_TOB_BCN_i, XTOB_BCN_i, TOB_BCN_i : std_logic_vector(11 downto 0);

   signal probe0 :  STD_LOGIC_VECTOR(19 DOWNTO 0);

   signal bcn_cntr_i :std_logic_vector(11 downto 0);

   --  ####### Mark signals  ########

   attribute keep                      : string;

   attribute max_fanout                : integer;

   attribute keep of sel_data_in       : signal is "true";

   attribute max_fanout of sel_data_in : signal is 30;

   --   #######################################


 begin


   -----------------------------------------------------------------

   -- data alignment block

   ------------------------------------------------------------------

   --- data from the rx of the mgt


   mgt_data_int <= (00 => MGT_Data(00).gt0_rxdata_out, 01 => MGT_Data(00).gt1_rxdata_out, 02 => MGT_Data(00).gt2_rxdata_out, 03 => MGT_Data(00).gt3_rxdata_out,

                    04 => MGT_Data(01).gt0_rxdata_out, 05 => MGT_Data(01).gt1_rxdata_out, 06 => MGT_Data(01).gt2_rxdata_out, 07 => MGT_Data(01).gt3_rxdata_out,

                    08 => MGT_Data(02).gt0_rxdata_out, 09 => MGT_Data(02).gt1_rxdata_out, 10 => MGT_Data(02).gt2_rxdata_out, 11 => MGT_Data(02).gt3_rxdata_out,

                    12 => MGT_Data(03).gt0_rxdata_out, 13 => MGT_Data(03).gt1_rxdata_out, 14 => MGT_Data(03).gt2_rxdata_out, 15 => MGT_Data(03).gt3_rxdata_out,

                    16 => MGT_Data(04).gt0_rxdata_out, 17 => MGT_Data(04).gt1_rxdata_out, 18 => MGT_Data(04).gt2_rxdata_out, 19 => MGT_Data(04).gt3_rxdata_out,

                    20 => MGT_Data(05).gt0_rxdata_out, 21 => MGT_Data(05).gt1_rxdata_out, 22 => MGT_Data(05).gt2_rxdata_out, 23 => MGT_Data(05).gt3_rxdata_out,

                    24 => MGT_Data(06).gt0_rxdata_out, 25 => MGT_Data(06).gt1_rxdata_out, 26 => MGT_Data(06).gt2_rxdata_out, 27 => MGT_Data(06).gt3_rxdata_out,

                    28 => MGT_Data(07).gt0_rxdata_out, 29 => MGT_Data(07).gt1_rxdata_out, 30 => MGT_Data(07).gt2_rxdata_out, 31 => MGT_Data(07).gt3_rxdata_out,

                    32 => MGT_Data(08).gt0_rxdata_out, 33 => MGT_Data(08).gt1_rxdata_out, 34 => MGT_Data(08).gt2_rxdata_out, 35 => MGT_Data(08).gt3_rxdata_out,

                    36 => MGT_Data(09).gt0_rxdata_out, 37 => MGT_Data(09).gt1_rxdata_out, 38 => MGT_Data(09).gt2_rxdata_out, 39 => MGT_Data(09).gt3_rxdata_out,

                    40 => MGT_Data(10).gt0_rxdata_out, 41 => MGT_Data(10).gt1_rxdata_out, 42 => MGT_Data(10).gt2_rxdata_out, 43 => MGT_Data(10).gt3_rxdata_out,

                    44 => MGT_Data(11).gt0_rxdata_out, 45 => MGT_Data(11).gt1_rxdata_out, 46 => MGT_Data(11).gt2_rxdata_out, 47 => MGT_Data(11).gt3_rxdata_out,

                    48 => MGT_Data(12).gt0_rxdata_out, 49 => MGT_Data(12).gt1_rxdata_out, 50 => MGT_Data(12).gt2_rxdata_out, 51 => MGT_Data(12).gt3_rxdata_out,

                    52 => MGT_Data(13).gt0_rxdata_out, 53 => MGT_Data(13).gt1_rxdata_out, 54 => MGT_Data(13).gt2_rxdata_out, 55 => MGT_Data(13).gt3_rxdata_out,

                    56 => MGT_Data(14).gt0_rxdata_out, 57 => MGT_Data(14).gt1_rxdata_out, 58 => MGT_Data(14).gt2_rxdata_out, 59 => MGT_Data(14).gt3_rxdata_out,

                    60 => MGT_Data(15).gt0_rxdata_out, 61 => MGT_Data(15).gt1_rxdata_out, 62 => MGT_Data(15).gt2_rxdata_out, 63 => MGT_Data(15).gt3_rxdata_out);


   --- data from the playback ram

   ram_data_int <= (00 => ram_data_mgt0(227 downto 0 ),   01 => ram_data_mgt1(227 downto 0),     02 => ram_data_mgt2(227 downto 0),     03 => ram_data_mgt3(227 downto 0),

                    04 => ram_data_mgt0(455 downto 228) , 05 => ram_data_mgt1(455 downto 228),   06 => ram_data_mgt2(455 downto 228),   07 => ram_data_mgt3(455 downto 228),

                    08 => ram_data_mgt0(683 downto 456) , 09 => ram_data_mgt1(683 downto 456),   10 => ram_data_mgt2(683 downto 456),   11 => ram_data_mgt3(683 downto 456),

                    12 => ram_data_mgt0(911 downto 684) , 13 => ram_data_mgt1(911 downto 684),   14 => ram_data_mgt2(911 downto 684),   15 => ram_data_mgt3(911 downto 684),

                    16 => ram_data_mgt0(1139 downto 912) ,17 => ram_data_mgt1(1139 downto 912),  18 => ram_data_mgt2(1139 downto 912),  19 => ram_data_mgt3(1139 downto 912),

                    20 => ram_data_mgt0(1367 downto 1140),21 => ram_data_mgt1(1367 downto 1140), 22 => ram_data_mgt2(1367 downto 1140), 23 => ram_data_mgt3(1367 downto 1140),

                    24 => ram_data_mgt0(1595 downto 1368),25 => ram_data_mgt1(1595 downto 1368), 26 => ram_data_mgt2(1595 downto 1368), 27 => ram_data_mgt3(1595 downto 1368),

                    28 => ram_data_mgt0(1823 downto 1596),29 => ram_data_mgt1(1823 downto 1596), 30 => ram_data_mgt2(1823 downto 1596), 31 => ram_data_mgt3(1823 downto 1596),

                    32 => ram_data_mgt0(2051 downto 1824),33 => ram_data_mgt1(2051 downto 1824), 34 => ram_data_mgt2(2051 downto 1824), 35 => ram_data_mgt3(2051 downto 1824),

                    36 => ram_data_mgt0(2279 downto 2052),37 => ram_data_mgt1(2279 downto 2052), 38 => ram_data_mgt2(2279 downto 2052), 39 => ram_data_mgt3(2279 downto 2052),

                    40 => ram_data_mgt0(2507 downto 2280),41 => ram_data_mgt1(2507 downto 2280), 42 => ram_data_mgt2(2507 downto 2280), 43 => ram_data_mgt3(2507 downto 2280),

                    44 => ram_data_mgt0(2735 downto 2508),45 => ram_data_mgt1(2735 downto 2508), 46 => ram_data_mgt2(2735 downto 2508), 47 => ram_data_mgt3(2735 downto 2508),

                    48 => ram_data_mgt0(2963 downto 2736),49 => ram_data_mgt1(2963 downto 2736), 50 => ram_data_mgt2(2963 downto 2736), 51 => ram_data_mgt3(2963 downto 2736),

                    52 => ram_data_mgt0(3191 downto 2964),53 => ram_data_mgt1(3191 downto 2964), 54 => ram_data_mgt2(3191 downto 2964), 55 => ram_data_mgt3(3191 downto 2964),

                    56 => ram_data_mgt0(3419 downto 3192),57 => ram_data_mgt1(3419 downto 3192), 58 => ram_data_mgt2(3419 downto 3192), 59 => ram_data_mgt3(3419 downto 3192),

                    60 => ram_data_mgt0(3647 downto 3420),61 => ram_data_mgt1(3647 downto 3420), 62 => ram_data_mgt2(3647 downto 3420), 63 => ram_data_mgt3(3647 downto 3420));


   data_alignment_block : entity work.data_alignment

     generic map(n_channels  => n_channels,

                 FPGA_NUMBER => FPGA_NUMBER)

     port map(

       TTC_clk           => ttc_clk,       -- 40MHz clock

       clk280            => clk280,        -- generated 280MHz clock

       rx_clk280         => rx_clk280,     -- rx_clks

       MGT_Commadet      => MGT_Commadet,

       enable_mgt        => enable_mgt,

       BC_Reg_sel        => BC_Reg_sel,

       mux_sel           => mux_sel,

       sel_bcn_or_bc_cnt => sel_bcn_or_bc_cnt,

       pseudo_orbit      => pseudo_orbit,

       start             => start,

       start_pulse_rst   => start_pulse_rst,

       rx_resetdone      => rx_resetdone,

       reset             => reset,

       DataToAlgo        => algo_in,

       RAW_data          => RAW_data,      -- raw data of 49 x 227

       bc_cntr_0         => bc_cntr_0,

       bc_cntr_1         => bc_cntr_1,

       bc_cntr_2         => bc_cntr_2,

       bc_cntr_3         => bc_cntr_3,

       bc_mux_cntr_0     => bc_mux_cntr_0,

       bc_mux_cntr_1     => bc_mux_cntr_1,

       bc_mux_cntr_2     => bc_mux_cntr_2,

       bc_mux_cntr_3     => bc_mux_cntr_3,

       bcn_synch         => bcn_synch,

       crc_error_chan    => crc_error_chan,

       data_readout_0    => data_readout_0,

       data_readout_1    => data_readout_1,

       data_readout_2    => data_readout_2,

       data_readout_3    => data_readout_3,

       delay_num         => delay_num,     -- for debuging

       Reg224_latch      => Reg224_latch,  -- for debuging

       ttc_pipe          => ttc_pipe,      -- for debuging

       delay_latch       => delay_latch,   --for debuging

       eFEXPosition      => eFEXPosition,

       sel_data_in       => sel_data_in,

       ram_data          => ram_data_int,

       MGT_data          => mgt_data_int,

       align_frame       => align_frame,

       disperr_error     => disperr_error,

       notable_error     => notable_error


       );


   --------------------------------------------------------------

   -- algorithm block

   --------------------------------------------------------------

   algorithm_block : entity algolib.IPBusTopAlgoModule

     generic map(ENCODING_MODE   => ENCODING_MODE,

                 USE_INPUT_RAM   => ENABLE_INPUT_RAM,

                 EFEX_POSITION   => EFEX_POSITION,

                 USE_OUTPUT_RAMS => ENABLE_OUTPUT_RAMS,

                 FPGA            => FPGA_NUMBER,

                 EG_ALGO_VERSION => EG_ALGO_VERSION,

                 TAU_ALGO_VERSION => TAU_ALGO_VERSION)

     port map(

       CLk200             => clk200,

       CLK280             => clk280,

       In_load            => in_load,

       ipb_clk            => ipb_clk,

       ipb_rst            => ipb_rst,

       ipb_in             => ipb_in_algo,

       ipb_out            => ipb_out_algo,

       -- out general ports

       OUT_eFEXPosition   => eFEXPosition,

       --algorithm data

       --IN_BCID            => BCID_int,

       IN_Data            => algo_in,

       IN_BCN             => bcn_cntr_i,

       --out ports eg

       OUT_eg_Sync        => eg_Sync,

       OUT_eg_Valid       => open,

       OUT_eg_TOB         => eg_TOB,

       OUT_BCN_XTOB       => XTOB_BCN_i,

       OUT_eg_Sync_XTOB   => eg_XSync,

       OUT_tau_Sync_XTOB  => tau_XSync,

       OUT_eg_XTOB        => eg_XTOB,

       OUT_tau_XTOB       => tau_XTOB,

       OUT_eg_Valid_XTOB  => eg_XValid,

       OUT_tau_Valid_XTOB => tau_XValid,

       OUT_BCN_TOB        => TOB_BCN_i,

       -- out ports tau

       OUT_tau_Sync       => open,

       OUT_tau_Valid      => open,

       OUT_tau_TOB        => tau_TOB

       );


   OUT_eg_Sync  <= eg_XSync;

   OUT_eg_Valid <= eg_XValid;

   OUT_eg_XTOB  <= eg_XTOB;


   OUT_tau_Sync  <= tau_XSync;

   OUT_tau_Valid <= tau_XValid;

   OUT_tau_XTOB  <= tau_XTOB;


   Sorting_Module : entity algolib.IPBusTopSortingModule

   generic map (

   USE_INPUT_RAM => ENABLE_SORTING_INPUT_RAM,

   USE_OUTPUT_RAM => ENABLE_SORTING_OUTPUT_RAM)

     port map (

       CLK           => clk280,

       IN_eg_Data    => eg_TOB,

       IN_tau_Data   => tau_TOB,

       IN_BCN        => TOB_BCN_i,

       IN_Sync       => eg_Sync,

       ipb_clk       => ipb_clk,

       ipb_rst       => ipb_rst,

       ipb_in        => ipb_in_sorting,

       ipb_out       => ipb_out_sorting,

       OUT_BCN       => sorted_TOB_BCN_i,

       OUT_eg_Sync   => OUT_sorted_eg_Sync,

       OUT_eg_Valid  => OUT_sorted_eg_Valid,

       OUT_eg_TOB    => OUT_sorted_eg_TOB,

       OUT_tau_Sync  => OUT_sorted_tau_Sync,

       OUT_tau_Valid => OUT_sorted_tau_Valid,

       OUT_tau_TOB   => OUT_sorted_tau_TOB);


   OUT_XTOB_BCN <= XTOB_BCN_i;

   OUT_TOB_BCN  <= sorted_TOB_BCN_i;


   --BCID_int_ila  <= X"000000" & '0' & BCID_int(0);

   --TOB_BCID_ila  <= X"000000" & '0' & sorted_TOB_BCID_i;

   --XTOB_BCID_ila <= X"000000" & '0' & XTOB_BCID_i;


   --U1_TOB_Delay_ila : ila_ipbus_fabric_rd_wr

   --PORT MAP (

   --      clk    =>  CLk280,

   --      probe0 =>  BCID_int_ila,       -- 32b

   --      probe1 =>  OUT_TOB_BCID_ila,  -- 32b

   --      probe2 =>  (others => '0'),   -- 1b

   --      probe3 =>  (others => '0'),           -- 1b

   --      probe4 =>  (others => '0') ,   -- 1b

   --      probe5 =>  OUT_XTOB_BCID_ila,  -- 32b

   --      probe6 =>  (others => '0'),        -- 32b

   --      probe7 =>   (others => '0'),             -- 1b

   --      probe8 =>   (others => '0') ,       -- 1b

   --    probe9 =>   (others => '0')              -- 1b

   --);

   tob_bcn_cntr : entity  infrastructure_lib.local_bcn_counter

   port map (

       clk              => ttc_clk,

       reset            => reset,

       bcr              => bcr_in,

       orbit_length     => ttc_orbit_length_reg,

       bcmux_value_sync => bcmuxvalue_sych_reg,

       bcn_cntr         => bcn_cntr_i

       );


 --ram_ila : ila_inputRam

 --PORT MAP (

 --clk   => ttc_clk,

 --    probe0(6 downto 0) => BCID_int(0),

 --    probe0(18 downto 7) => bcn_cntr_i,

 --    probe0(19) =>  bcr_in

 --  );


 end Behavioral;

AlgoDataTypes
External data-types and functions.
Definition: AlgoDataTypes.vhd:15

AlgoDataTypes.AlgoOutput
(   OUTPUT_TOBS- 1 downto  0)  AlgoTriggerObject AlgoOutput
Algorithm OUTPUT port.
Definition: AlgoDataTypes.vhd:126

AlgoDataTypes.AlgoInput
(   INPUT_COLUMNS- 1 downto  0)  AlgoColumn AlgoInput
Algorithm INPUT port.
Definition: AlgoDataTypes.vhd:109

AlgoDataTypes.AlgoTriggerObject
std_logic_vector(   OUT_TOB_WIDTH- 1 downto  0) AlgoTriggerObject
Algorithm Trigger Object TOB.
Definition: AlgoDataTypes.vhd:120

AlgoDataTypes.AlgoXOutput
(   OUTPUT_TOBS- 1 downto  0)  AlgoXTriggerObject AlgoXOutput
Algorithm XOUTPUT port.
Definition: AlgoDataTypes.vhd:128

DataTypes
Definition: DataTypes.vhd:6

EfexDataFormats
eFEX data-types and functions
Definition: efex_data_formats.vhd:352

IPBusTopAlgoModule
Top feature extracting algorithm module with IPBus interface.
Definition: IPBusTopAlgoModule.vhd:72

IPBusTopAlgoModule.ipb_rst
in ipb_rst std_logic
IPBus reset.
Definition: IPBusTopAlgoModule.vhd:85

IPBusTopAlgoModule.OUT_eg_Valid
out OUT_eg_Valid std_logic_vector(   OUTPUT_TOBS- 1 downto  0)
Output data valid, high when correspondent output data are valid.
Definition: IPBusTopAlgoModule.vhd:93

IPBusTopAlgoModule.OUT_eg_Valid_XTOB
out OUT_eg_Valid_XTOB std_logic_vector(   OUTPUT_TOBS- 1 downto  0)
Output data valid, high when correspondent output data are valid.
Definition: IPBusTopAlgoModule.vhd:102

IPBusTopAlgoModule.OUT_BCN_TOB
out OUT_BCN_TOB std_logic_vector( 11 downto  0)
Delayed crossing number as decoded from input data.
Definition: IPBusTopAlgoModule.vhd:105

IPBusTopAlgoModule.CLK280
in CLK280 std_logic
280 MHz clock, used in the output stage
Definition: IPBusTopAlgoModule.vhd:82

IPBusTopAlgoModule.OUT_tau_TOB
out OUT_tau_TOB AlgoOutput
Algorithm external data structure, defined in AlgoDataTypes.vhd.
Definition: IPBusTopAlgoModule.vhd:109

IPBusTopAlgoModule.OUT_tau_XTOB
out OUT_tau_XTOB AlgoXOutput
Algorithm external XTOB data structure, defined in AlgoDataTypes.vhd.
Definition: IPBusTopAlgoModule.vhd:101

IPBusTopAlgoModule.OUT_eg_XTOB
out OUT_eg_XTOB AlgoXOutput
Algorithm external XTOB data structure, defined in AlgoDataTypes.vhd.
Definition: IPBusTopAlgoModule.vhd:100

IPBusTopAlgoModule.OUT_eg_Sync
out OUT_eg_Sync std_logic
Output sync, high on the first clock cycle of the BC.
Definition: IPBusTopAlgoModule.vhd:92

IPBusTopAlgoModule.OUT_tau_Valid
out OUT_tau_Valid std_logic_vector(   OUTPUT_TOBS- 1 downto  0)
Output data valid, high when correspondent output data are valid.
Definition: IPBusTopAlgoModule.vhd:108

IPBusTopAlgoModule.IN_Data
in IN_Data AlgoInput
Algorithm external data structure, defined in AlgoDataTypes.vhd.
Definition: IPBusTopAlgoModule.vhd:90

IPBusTopAlgoModule.OUT_tau_Sync
out OUT_tau_Sync std_logic
Output sync, high on the first clock cycle of the BC.
Definition: IPBusTopAlgoModule.vhd:107

IPBusTopAlgoModule.ipb_clk
in ipb_clk std_logic
IPBus clk.
Definition: IPBusTopAlgoModule.vhd:84

IPBusTopAlgoModule.ipb_out
out ipb_out ipb_rbus
IPBus read bus.
Definition: IPBusTopAlgoModule.vhd:87

IPBusTopAlgoModule.OUT_eg_TOB
out OUT_eg_TOB AlgoOutput
Algorithm external data structure, defined in AlgoDataTypes.vhd.
Definition: IPBusTopAlgoModule.vhd:95

IPBusTopAlgoModule.ipb_in
in ipb_in ipb_wbus
IPBus write bus.
Definition: IPBusTopAlgoModule.vhd:86

IPBusTopAlgoModule.OUT_eFEXPosition
out OUT_eFEXPosition std_logic_vector( 31 downto  0)
Geographic position of eFEX Module, to be used in the mapping logic.
Definition: IPBusTopAlgoModule.vhd:88

IPBusTopAlgoModule.OUT_BCN_XTOB
out OUT_BCN_XTOB std_logic_vector( 11 downto  0)
Delayed crossing number as decoded from input data.
Definition: IPBusTopAlgoModule.vhd:97

IPBusTopAlgoModule.OUT_tau_Valid_XTOB
out OUT_tau_Valid_XTOB std_logic_vector(   OUTPUT_TOBS- 1 downto  0)
Output data valid, high when correspondent output data are valid.
Definition: IPBusTopAlgoModule.vhd:103

IPBusTopSortingModule
Top of TOB sorting module with IPBus interface.
Definition: IPBusTopSortingModule.vhd:27

TOB_rdout_ip_pkg
Definition: TOB_rdout_ip_pkg.vhd:34

data_alignment
Data Alignment module.
Definition: data_alignment.vhd:24

data_alignment.eFEXPosition
in eFEXPosition std_logic_vector( 31 downto  0)
Geographical position of eFEX module for dynamic mapping.
Definition: data_alignment.vhd:62

data_path_block.Behavioral
Data path block.
Definition: data_path_block.vhd:151

data_path_block.Behavioral.eFEXPosition
std_logic_vector( 31 downto  0) eFEXPosition
Geographic position of eFEX Module, for the mapping logic.
Definition: data_path_block.vhd:176

data_path_block
Data path block.
Definition: data_path_block.vhd:45

data_path_block.in_load
in in_load std_logic
clk 40MHz, 20% duty cycle
Definition: data_path_block.vhd:62

data_path_block.ttc_clk
in ttc_clk std_logic
40 MHz clk
Definition: data_path_block.vhd:61

data_path_block.OUT_sorted_eg_TOB
out OUT_sorted_eg_TOB AlgoTriggerObject
Sorted eg TOB 32bit.
Definition: data_path_block.vhd:112

data_path_block.RAW_data
out RAW_data RAW_data_227_type
RAW data to Readout.
Definition: data_path_block.vhd:91

data_path_block.reset
in reset std_logic
syncronous reset used in data_alignment
Definition: data_path_block.vhd:60

data_path_block.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: data_path_block.vhd:65

data_path_block.OUT_TOB_BCN
out OUT_TOB_BCN std_logic_vector( 11 downto  0)
BCN @280 MHZ referring to 7 TOBS in the BC.
Definition: data_path_block.vhd:120

data_path_block.OUT_eg_Valid
out OUT_eg_Valid std_logic_vector(   OUTPUT_TOBS- 1 downto  0)
Valid signal for eg XTOBS @200MHz.
Definition: data_path_block.vhd:95

data_path_block.rx_clk280
in rx_clk280 std_logic_vector(   n_channels- 1 downto  0)
MGT clocks.
Definition: data_path_block.vhd:58

data_path_block.OUT_sorted_eg_Valid
out OUT_sorted_eg_Valid std_logic
Sorted TOB valid @280.
Definition: data_path_block.vhd:114

data_path_block.OUT_sorted_tau_Valid
out OUT_sorted_tau_Valid std_logic
Sorted TOB valid @280.
Definition: data_path_block.vhd:119

data_path_block.BC_Reg_sel
in BC_Reg_sel std_logic_vector( 255 downto  0)
16-b BC MUX select for 16 Quads
Definition: data_path_block.vhd:75

data_path_block.OUT_XTOB_BCN
out OUT_XTOB_BCN std_logic_vector( 11 downto  0)
XTOB BCN @200 MHZ referring to 5 TOBS in the BC.
Definition: data_path_block.vhd:109

data_path_block.OUT_sorted_tau_Sync
out OUT_sorted_tau_Sync std_logic
Sorted TOB synch @280 marking first TOB of 7.
Definition: data_path_block.vhd:118

data_path_block.OUT_sorted_tau_TOB
out OUT_sorted_tau_TOB AlgoTriggerObject
Sorted eg TOB 32bit.
Definition: data_path_block.vhd:117

data_path_block.ipb_in_algo
in ipb_in_algo ipb_wbus
ipbus connection for algorithm
Definition: data_path_block.vhd:66

data_path_block.ipb_out_algo
out ipb_out_algo ipb_rbus
ipbus connection for algorithm
Definition: data_path_block.vhd:67

data_path_block.OUT_tau_XTOB
out OUT_tau_XTOB AlgoXOutput
tau XTOBS 8 x 64bit @200MHz
Definition: data_path_block.vhd:106

data_path_block.mux_sel
in mux_sel std_logic_vector( 255 downto  0)
16-b 1st stage MUX select for 16 Quads
Definition: data_path_block.vhd:76

data_path_block.OUT_eg_XTOB
out OUT_eg_XTOB AlgoXOutput
eg XTOBS 8 x 64bit @200MHz
Definition: data_path_block.vhd:99

data_path_block.OUT_eg_Sync
out OUT_eg_Sync std_logic
Sync signal for XTOBS @200MHz marking the first XTOB of 5.
Definition: data_path_block.vhd:97

data_path_block.ipb_in_sorting
in ipb_in_sorting ipb_wbus
ipbus connection for local TOB sorting
Definition: data_path_block.vhd:68

data_path_block.OUT_tau_Valid
out OUT_tau_Valid std_logic_vector(   OUTPUT_TOBS- 1 downto  0)
Valid signal for eg XTOBS @200MHz.
Definition: data_path_block.vhd:102

data_path_block.OUT_tau_Sync
out OUT_tau_Sync std_logic
Sync signal for XTOBS @200MHz marking the first XTOB of 5.
Definition: data_path_block.vhd:104

data_path_block.clk280
in clk280 std_logic
Used in the output stage of the algorithm.
Definition: data_path_block.vhd:59

data_path_block.rx_resetdone
in rx_resetdone std_logic_vector(   n_channels- 1 downto  0)
reset done from GMTs
Definition: data_path_block.vhd:78

data_path_block.ipb_clk
in ipb_clk std_logic
ipbus clock
Definition: data_path_block.vhd:64

data_path_block.ipb_out_sorting
out ipb_out_sorting ipb_rbus
ipbus connection for local TOB sorting
Definition: data_path_block.vhd:69

data_path_block.OUT_sorted_eg_Sync
out OUT_sorted_eg_Sync std_logic
Sorted TOB synch @280 marking first TOB of 7.
Definition: data_path_block.vhd:113

data_path_block.sel_bcn_or_bc_cnt
in sel_bcn_or_bc_cnt std_logic
selects between real data BC value (1) and BC delay counter (0) to ipbus
Definition: data_path_block.vhd:73

data_path_block.enable_mgt
in enable_mgt std_logic_vector(   n_channels- 1 downto  0)
MGT enable.
Definition: data_path_block.vhd:77

data_path_block.pseudo_orbit
out pseudo_orbit std_logic
Pulse generated when 5-bit BCN is 00000.
Definition: data_path_block.vhd:74

data_type_pkg
Definition: data_type_pkg.vhd:34

local_bcn_counter
Definition: local_bcn_counter.vhd:5

mgt_type
Definition: mgt_type_pkg.vhd:4

synch_type
Definition: synch_type_pkg.vhd:23