IPBusTopSortingModule Entity Reference

Top of TOB sorting module with IPBus interface. More...

Inheritance diagram for IPBusTopSortingModule:

Entities
Behavioral	architecture
	Top of TOB sorting module with IPBus interface. More...

Libraries
IEEE
work
ipbus_lib
infrastructure_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
ipbus_decode_efex_sorting
DataTypes	Package <DataTypes>
AlgoDataTypes	Package <AlgoDataTypes>
ipbus_reg_types
ipbus

Generics
USE_INPUT_RAM	boolean
USE_OUTPUT_RAM	boolean

Ports
CLK	in	std_logic
IN_eg_Data	in	AlgoOutput
IN_tau_Data	in	AlgoOutput
IN_BCN	in	std_logic_vector ( 11 downto 0 )
IN_Sync	in	std_logic
ipb_clk	in	std_logic
ipb_rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
OUT_BCN	out	std_logic_vector ( 11 downto 0 )
OUT_eg_Sync	out	std_logic
OUT_eg_Valid	out	std_logic
OUT_eg_TOB	out	AlgoTriggerObject
OUT_tau_Sync	out	std_logic
OUT_tau_Valid	out	std_logic
OUT_tau_TOB	out	AlgoTriggerObject

Detailed Description

Top of TOB sorting module with IPBus interface.

This module is an IPBus-capable wrapper of the TopSorting Modules. It contains 2 8-input sorting modules, one for e/g one for tau, 2 input and 2 output spyRAMs, all ipbus controlled.

Author

Francesco Gonnella

Definition at line 27 of file IPBusTopSortingModule.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/IPBusTopSortingModule.vhd