eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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IPBusTopSortingModule.vhd
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1 
8 
9 library IEEE;
10 use IEEE.STD_LOGIC_1164.all;
11 use IEEE.NUMERIC_STD.all;
12 
13 library work;
14 use work.ipbus_decode_efex_sorting.all;
15 
16 use work.DataTypes.all;
17 use work.AlgoDataTypes.all;
18 
19 library ipbus_lib;
20 use ipbus_lib.ipbus_reg_types.all;
21 
22 use ipbus_lib.ipbus.all;
23 
24 library infrastructure_lib;
25 
27 entity IPBusTopSortingModule is
28  generic (USE_INPUT_RAM : boolean;
29  USE_OUTPUT_RAM : boolean);
30  port (CLK : in std_logic;
31 
32  IN_eg_Data : in AlgoOutput;
33  IN_tau_Data : in AlgoOutput;
34  IN_BCN : in std_logic_vector(11 downto 0);
35  IN_Sync : in std_logic;
36 
37  --IPBus connection
38  ipb_clk : in std_logic;
39  ipb_rst : in std_logic;
40  ipb_in : in ipb_wbus;
41  ipb_out : out ipb_rbus;
42 
43 
44  OUT_BCN : out std_logic_vector(11 downto 0);
45  OUT_eg_Sync : out std_logic;
46  OUT_eg_Valid : out std_logic;
47  OUT_eg_TOB : out AlgoTriggerObject;
48 
49  OUT_tau_Sync : out std_logic;
50  OUT_tau_Valid : out std_logic;
51  OUT_tau_TOB : out AlgoTriggerObject);
52 
53 end IPBusTopSortingModule;
54 
56 architecture Behavioral of IPBusTopSortingModule is
57  constant N_CTRL : positive := 4; --number of control reg
58  constant N_STAT : positive := 4; --number of status reg
59 
60  -- Algorithm signal
61 
62 -- IPBus signals
63  signal ipb_to_slaves : ipb_wbus_array(N_SLAVES - 1 downto 0);
64  signal ipb_from_slaves : ipb_rbus_array(N_SLAVES - 1 downto 0) := (others => IPB_RBUS_NULL);
65 
66  signal write_reg : ipb_reg_v(N_STAT - 1 downto 0) := (others => (others => '0'));
67  signal read_reg : ipb_reg_v(N_CTRL - 1 downto 0);
68 
69 -- registers
70  signal regControl_eg : AlgoRegister;
71  signal regStatus_eg : AlgoRegister;
72 
73  signal regControl_tau : AlgoRegister;
74  signal regStatus_tau : AlgoRegister;
75 
76 
77 
78  signal regDebug : AlgoRegisters(3 downto 0); --to change
79 
80  signal AlgoStart : std_logic;
81  signal AlgoData_eg : AlgoTriggerObjects(7 downto 0);
82  signal AlgoData_tau : AlgoTriggerObjects(7 downto 0);
83 
84  signal SortStart_eg : std_logic;
85  signal SortWrite_eg : std_logic;
86  signal SortData_eg : AlgoTriggerObject;
87  signal SortedData_eg : AlgoTriggerObject;
88  signal SortingData_eg : AlgoTriggerObjects(7 downto 0);
89 
90  signal SortStart_tau : std_logic;
91  signal SortWrite_tau : std_logic;
92  signal SortData_tau : AlgoTriggerObject;
93  signal SortedData_tau : AlgoTriggerObject;
94  signal SortingData_tau : AlgoTriggerObjects(7 downto 0);
95 
96 -- spy RAMs
97  signal InputRAMOut_eg, InputRAMOut_tau : AlgoOutput;
98  signal FakeInputEnable_eg, FakeInputEnable_tau : std_logic := '0';
99  signal SpyInputEnable_eg, SpyInputEnable_tau : std_logic := '0';
100 
101  signal OutputRAMOut_eg, OutputRAMOut_tau : AlgoTriggerObject;
102  signal FakeOutputEnable_eg, FakeOutputEnable_tau : std_logic := '0';
103  signal SpyOutputEnable_eg, SpyOutputEnable_tau : std_logic := '0';
104  signal SpyBCN_eg, SpyBCN_tau : std_logic := '0';
105  signal SpyBCN_out_eg, SpyBCN_out_tau : std_logic := '0';
106  signal BCN_int : std_logic_vector(11 downto 0);
107 
108 begin
109 
110  IPBUS_FABRIC : entity ipbus_lib.ipbus_fabric_sel
111  generic map (
112  NSLV => N_SLAVES, --defined in ipbus_sel_address_table_SORTING
113  SEL_WIDTH => IPBUS_SEL_WIDTH)
114  port map (
115  sel => ipbus_sel_efex_sorting(ipb_in.ipb_addr), --function defined in ipbus_sel_address_table_SORTING
116 
117  ipb_in => ipb_in,
118  ipb_out => ipb_out,
119  ipb_to_slaves => ipb_to_slaves,
120  ipb_from_slaves => ipb_from_slaves);
121 
122  IPBUS_SORTING_REGISTERS : entity ipbus_lib.ipbus_ctrlreg_v
123  generic map (
124  N_CTRL => N_CTRL, --number of control reg
125  N_STAT => N_STAT) --number of status reg
126  port map (
127  clk => ipb_clk,
128  reset => ipb_rst,
129  ipbus_in => ipb_to_slaves(N_SLV_SORTING_REGISTERS),
130  ipbus_out => ipb_from_slaves(N_SLV_SORTING_REGISTERS),
131  d => write_reg,
132  q => read_reg,
133 -- qmask => (others => '0'),
134  stb => open);
135 
136 
137  -- a generic being tau/eg should be implemented to use different sorting
138  -- priorities for the two algos
139 
140  -----------------------------------------------------------------------------
141  -- Electromagnetic TOB sorting
142  -----------------------------------------------------------------------------
143  SortingData_eg <= to_AlgoTriggerObjects(IN_eg_Data);
144 
145 --input MUX: real data/ data from input RAM
146  AlgoData_eg <= to_AlgoTriggerObjects(InputRAMOut_eg) when FakeInputEnable_eg = '1' else SortingData_eg;
147 
148 EG_IN_IF: if USE_INPUT_RAM generate
149  eg_inputRAM : entity work.ipbus_sorting_inputRAM_wrapper
150  port map (
151  clk_ipb => ipb_clk,
152  rst => ipb_rst,
153  ipb_in => ipb_to_slaves(N_SLV_SORTING_INPUT_RAM_EG),
154  ipb_out => ipb_from_slaves(N_SLV_SORTING_INPUT_RAM_EG),
155 
156  SortingIn => IN_eg_Data,
157  BCNIn => IN_BCN,
158  SpyBCNIN => SpyBCN_eg,
159  rclk => CLK,
160  Sync => AlgoStart,
161  we => SpyInputEnable_eg,
162  SortingOut => InputRAMOut_eg);
163 
164  else generate
165  ipb_from_slaves(N_SLV_SORTING_INPUT_RAM_EG) <= IPB_RBUS_NULL;
166  InputRAMOut_eg <= (others => (others => '0'));
167 
168  end generate;
169 
170 
171  TopSorting_eg : entity work.TopSortingModule
172  generic map (
173  STAGE => 3)
174  port map (
175  CLK => CLK,
176  IN_Control => regControl_eg,
177  OUT_Status => regStatus_eg,
178  IN_Start => AlgoStart,
179  IN_Data => AlgoData_eg,
180  OUT_Start => SortStart_eg,
181  OUT_Write => SortWrite_eg,
182  OUT_Data => SortData_eg);
183 
184 -- Conversion to external TOBs
185  SortedData_eg <= to_AlgoTriggerObject(SortData_eg);
186 
187 EG_OUT_IF: if USE_OUTPUT_RAM generate
188  eg_outputRAM : entity work.ipbus_sorting_outputRAM_wrapper
189  port map (
190  clk_ipb => ipb_clk,
191  rst => ipb_rst,
192  ipb_in => ipb_to_slaves(N_SLV_SORTING_OUTPUT_EG_RAM),
193  ipb_out => ipb_from_slaves(N_SLV_SORTING_OUTPUT_EG_RAM),
194 
195  SortedIn => SortedData_eg,
196  BCNIn => BCN_int,
197  SpyBCNIN => SpyBCN_out_eg,
198  rclk => CLK,
199  Sync => AlgoStart,
200  we => SpyOutputEnable_eg,
201  SortedOut => OutputRAMOut_eg);
202 
203  else generate
204  ipb_from_slaves(N_SLV_SORTING_OUTPUT_EG_RAM) <= IPB_RBUS_NULL;
205  OutputRAMOut_eg <= (others => '0');
206  end generate;
207 
208 --output MUX: real data/ data from output RAM
209  OUT_eg_TOB <= OutputRAMOut_eg when FakeOutputEnable_eg = '1' else SortedData_eg;
210  OUT_eg_Sync <= SortStart_eg;
211 -- data valid should be done better...
212  OUT_eg_Valid <= '1' when FakeOutputEnable_eg = '1' else SortWrite_eg;
213 
214  -----------------------------------------------------------------------------
215  -- Tau TOB sorting
216  -----------------------------------------------------------------------------
217  SortingData_tau <= to_AlgoTriggerObjects(IN_tau_Data);
218 
219 --input MUX: real data/ data from input RAM
220  AlgoData_tau <= to_AlgoTriggerObjects(InputRAMOut_tau) when FakeInputEnable_tau = '1' else SortingData_tau;
221 
222 TAU_IN_IF: if USE_INPUT_RAM generate
223  tau_inputRAM : entity work.ipbus_sorting_inputRAM_wrapper
224  port map (
225  clk_ipb => ipb_clk,
226  rst => ipb_rst,
227  ipb_in => ipb_to_slaves(N_SLV_SORTING_INPUT_RAM_TAU),
228  ipb_out => ipb_from_slaves(N_SLV_SORTING_INPUT_RAM_TAU),
229 
230  SortingIn => IN_tau_Data,
231  BCNIn => IN_BCN,
232  SpyBCNIN => SpyBCN_tau,
233  rclk => CLK,
234  Sync => AlgoStart,
235  we => SpyInputEnable_tau,
236  SortingOut => InputRAMOut_tau);
237  else generate
238  ipb_from_slaves(N_SLV_SORTING_INPUT_RAM_EG) <= IPB_RBUS_NULL;
239  InputRAMOut_tau <= (others => (others => '0'));
240  end generate;
241 
242 
243 
244  TopSorting_tau : entity work.TopSortingModule
245  generic map (
246  STAGE => 3)
247  port map (
248  CLK => CLK,
249  IN_Control => regControl_tau,
250  OUT_Status => regStatus_tau,
251  IN_Start => AlgoStart,
252  IN_Data => AlgoData_tau,
253  OUT_Start => SortStart_tau,
254  OUT_Write => SortWrite_tau,
255  OUT_Data => SortData_tau);
256 
257 -- Conversion to external TOBs
258  SortedData_tau <= to_AlgoTriggerObject(SortData_tau);
259 
260 TAU_OUT_IF: if USE_OUTPUT_RAM generate
261  tau_outputRAM : entity work.ipbus_sorting_outputRAM_wrapper
262  port map (
263  clk_ipb => ipb_clk,
264  rst => ipb_rst,
265  ipb_in => ipb_to_slaves(N_SLV_SORTING_OUTPUT_TAU_RAM),
266  ipb_out => ipb_from_slaves(N_SLV_SORTING_OUTPUT_TAU_RAM),
267 
268  SortedIn => SortedData_tau,
269  BCNIn => BCN_int,
270  SpyBCNIN => SpyBCN_out_tau,
271  rclk => CLK,
272  Sync => AlgoStart,
273  we => SpyOutputEnable_tau,
274  SortedOut => OutputRAMOut_tau);
275  else generate
276  ipb_from_slaves(N_SLV_SORTING_OUTPUT_TAU_RAM) <= IPB_RBUS_NULL;
277  OutputRAMOut_tau <= (others => '0');
278  end generate;
279 
280 
281  BCN_Delay : entity infrastructure_lib.GeneralDelay
282  generic map (
283  delay => 7,
284  size => 12)
285  port map (
286  clk => CLK,
287  data_in => IN_BCN,
288  data_out => BCN_int);
289 
290  OUT_BCN <= BCN_int;
291 
292 
293 
294 --output MUX: real data/ data from output RAM
295  OUT_tau_TOB <= OutputRAMOut_tau when FakeOutputEnable_tau = '1' else SortedData_tau;
296  OUT_tau_Sync <= SortStart_tau;
297 -- data valid should be done better...
298  OUT_tau_Valid <= '1' when FakeOutputEnable_tau = '1' else SortWrite_tau;
299 
300 
301 
302 
303 -- Sorting registers connection
304  regControl_eg <= read_reg(00);
305  regControl_tau <= read_reg(01);
306  regDebug(0) <= read_reg(02);
307  regDebug(1) <= read_reg(03);
308 
309  write_reg(0) <= regStatus_eg;
310  write_reg(1) <= regStatus_tau;
311  write_reg(2) <= regDebug(2);
312  write_reg(3) <= regDebug(3);
313 
314  AlgoStart <= IN_Sync;
315 
316 -- Sorting register funcionality
317  FakeInputEnable_eg <= regControl_eg(0);
318  SpyInputEnable_eg <= regControl_eg(1);
319  FakeOutputEnable_eg <= regControl_eg(2);
320  SpyOutputEnable_eg <= regControl_eg(3);
321  SpyBCN_eg <= regControl_eg(4);
322  SpyBCN_out_eg <= regControl_eg(5);
323 
324  FakeInputEnable_tau <= regControl_tau(0);
325  SpyInputEnable_tau <= regControl_tau(1);
326  FakeOutputEnable_tau <= regControl_tau(2);
327  SpyOutputEnable_tau <= regControl_tau(3);
328  SpyBCN_tau <= regControl_tau(4);
329  SpyBCN_out_tau <= regControl_tau(5);
330 
331 end architecture;
AlgoDataTypes
External data-types and functions.
Definition: AlgoDataTypes.vhd:15
AlgoDataTypes.AlgoOutput
( OUTPUT_TOBS- 1 downto 0) AlgoTriggerObject AlgoOutput
Algorithm OUTPUT port.
Definition: AlgoDataTypes.vhd:126
AlgoDataTypes.AlgoTriggerObjects
array(natural range <> ) of AlgoTriggerObject AlgoTriggerObjects
Algorithm OUTPUT port.
Definition: AlgoDataTypes.vhd:122
AlgoDataTypes.AlgoTriggerObject
std_logic_vector( OUT_TOB_WIDTH- 1 downto 0) AlgoTriggerObject
Algorithm Trigger Object TOB.
Definition: AlgoDataTypes.vhd:120
GeneralDelay
Shift register for data delay.
Definition: GeneralDelay.vhd:10
IPBusTopSortingModule.Behavioral
Top of TOB sorting module with IPBus interface.
Definition: IPBusTopSortingModule.vhd:56
IPBusTopSortingModule
Top of TOB sorting module with IPBus interface.
Definition: IPBusTopSortingModule.vhd:27
TopSortingModule
Top of TOB sorting module.
Definition: TopSortingModule.vhd:20
ipbus_sorting_inputRAM_wrapper
Definition: ipbus_sorting_inputRAM_wrapper.vhd:14
ipbus_sorting_outputRAM_wrapper
Definition: ipbus_sorting_outputRAM_wrapper.vhd:14
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