TopSortingModule Entity Reference

Top of TOB sorting module. More...

Inheritance diagram for TopSortingModule:

Entities
Behavioral	architecture
	Top of TOB sorting module. More...

Libraries
IEEE
work

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
DataTypes	Package <DataTypes>
AlgoDataTypes	Package <AlgoDataTypes>

Generics
STAGE	integer := 3
N_TOBS	integer := 5

Ports
CLK	in	std_logic
IN_Control	in	AlgoRegister
OUT_Status	out	AlgoRegister
IN_Start	in	std_logic
IN_Data	in	AlgoTriggerObjects ( ( 2 ** STAGE ) - 1 downto 0 )
OUT_Start	out	std_logic
OUT_Write	out	std_logic
OUT_Data	out	AlgoTriggerObject

Detailed Description

Top of TOB sorting module.

This module is a 3-stage TOB sorter. The input are 8 32-bit TOBs, the output is on 32-bit TOB. The clock frequency is 280 MHz. The OUT_Start signal marks the first of the 7 clock cycles on which the first output TOB is sent out (if any). The TOBs are valid only if the OUT_Write signal is high.

Author

Francesco Gonnella

Definition at line 20 of file TopSortingModule.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/TopSortingModule.vhd