Behavioral Architecture Reference

Top of TOB sorting module. More...

Processes
PROCESS_18	( CLK )
PROCESS_19	( CLK )

Signals
connector	AlgoTriggerObjects ( ( 2 ** ( stage+ 1 ) ) - 2 downto 0 )
start	std_logic_vector ( ( 2 ** ( stage+ 1 ) ) - 2 downto 0 )
writ	std_logic_vector ( ( 2 ** ( stage+ 1 ) ) - 2 downto 0 )

Instantiations
par_sorter	ParallelSorter <Entity ParallelSorter>
par_sorter	ParallelSorter <Entity ParallelSorter>

Detailed Description

Top of TOB sorting module.

This module is a 3-stage TOB sorter. The input are 8 32-bit TOBs, the output is on 32-bit TOB. The clock frequency is 280 MHz. The OUT_Start signal marks the first of the 7 clock cycles on which the first output TOB is sent out (if any). The TOBs are valid only if the OUT_Write signal is high.

Author

Francesco Gonnella

Definition at line 40 of file TopSortingModule.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/TopSortingModule.vhd