IPBusTopAlgoModule Entity Reference

Top feature extracting algorithm module with IPBus interface. More...

Inheritance diagram for IPBusTopAlgoModule:

Entities
Behavioral	architecture
	Top feature extracting algorithm module with IPBus interface. More...

Libraries
IEEE
	Use standard library.
ipbus_lib
	Use ipbus ibrary.
infrastructure_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
ipbus_decode_efex_algorithm
	Use ipbus address decode automatically generated from XML.
DataTypes	Package <DataTypes>
	Use internal algorithm data types and functions.
AlgoDataTypes	Package <AlgoDataTypes>
	Use external algorithm data types and functions.
ipbus_reg_types
	Use ipbus ibrary.
ipbus
	Use ipbus ibrary.
EfexDataFormats	Package <EfexDataFormats>

Generics
ENCODING_MODE	integer
USE_INPUT_RAM	boolean := false
EFEX_POSITION	integer := 0
USE_OUTPUT_RAMS	boolean := false
FPGA	integer := 1
EG_ALGO_VERSION	std_logic_vector ( 1 downto 0 )
TAU_ALGO_VERSION	std_logic_vector ( 1 downto 0 )

Ports
CLK200	in	std_logic
		200 MHz clock
CLK280	in	std_logic
		280 MHz clock, used in the output stage
IN_Load	in	std_logic
		40 MHz clock, 12% duty cycle
ipb_clk	in	std_logic
		IPBus clk.
ipb_rst	in	std_logic
		IPBus reset.
ipb_in	in	ipb_wbus
		IPBus write bus.
ipb_out	out	ipb_rbus
		IPBus read bus.
OUT_eFEXPosition	out	std_logic_vector ( 31 downto 0 )
		Geographic position of eFEX Module, to be used in the mapping logic.
IN_Data	in	AlgoInput
		Algorithm external data structure, defined in AlgoDataTypes.vhd.
IN_BCN	in	std_logic_vector ( 11 downto 0 )
OUT_eg_Sync	out	std_logic
		Output sync, high on the first clock cycle of the BC.
OUT_eg_Valid	out	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
		Output data valid, high when correspondent output data are valid.
OUT_eg_TOB	out	AlgoOutput
		Algorithm external data structure, defined in AlgoDataTypes.vhd.
OUT_BCN_XTOB	out	std_logic_vector ( 11 downto 0 )
		Delayed crossing number as decoded from input data.
OUT_eg_sync_XTOB	out	std_logic
OUT_tau_sync_XTOB	out	std_logic
OUT_eg_XTOB	out	AlgoXOutput
		Algorithm external XTOB data structure, defined in AlgoDataTypes.vhd.
OUT_tau_XTOB	out	AlgoXOutput
		Algorithm external XTOB data structure, defined in AlgoDataTypes.vhd.
OUT_eg_Valid_XTOB	out	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
		Output data valid, high when correspondent output data are valid.
OUT_tau_Valid_XTOB	out	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
		Output data valid, high when correspondent output data are valid.
OUT_BCN_TOB	out	std_logic_vector ( 11 downto 0 )
		Delayed crossing number as decoded from input data.
OUT_tau_Sync	out	std_logic
		Output sync, high on the first clock cycle of the BC.
OUT_tau_Valid	out	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
		Output data valid, high when correspondent output data are valid.
OUT_tau_TOB	out	AlgoOutput
		Algorithm external data structure, defined in AlgoDataTypes.vhd.

Detailed Description

Top feature extracting algorithm module with IPBus interface.

The feature extracting module runs at 200 MHz, i.e. 5 times faster than the BC frequency. So data belonging to a Bunch Crossing (BC) can be handled in 5 clock cycles. An eFEX FPGA handles 60 input Trigger Towers (TT) among which 40 are core towers, i.e. a TOB must be produced for each of them and 20 are used just as environment.

In order to produce 40 TOBs per BC, 40 independent Algorithm Cores (ACs) should process data in parallel. Thanks to the higher frequency, 8 ACs are enough to process data presented to the cores in 5 clock cycles. It is possible to handle a region of 0.7 Eta * 0.8 Phi.

In case the eFEX module is handling a border region in Eta, a number of environment-only TT must be used as core. This means that real data from the column at the far left end (or right) is not provided by the calorimeter. In this case, dummy data (e.g. all zeroes) are fed to the ACs. This module uses 2 clocks: 200 MHz and 280 MHz, plus a 40 MHz 12% duty cyle Load clock. The 200MHz, the Load and the 40MHz clocks must be in phase when the Load is high, as shown in figure.

            ┌───────┐       ┌───────┐       ┌───────┐       ┌───
 CLK40:    ─┘       └───────┘       └───────┘       └───────┘
            ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
 CLK200:   ─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─
            ┌┐              ┌┐              ┌┐              ┌┐
 Load:    ──┘└──────────────┘└──────────────┘└──────────────┘└──
          ──┬───────────────┬───────────────┬───────────────┬───
 Data:      │   DATA BC1    │   DATA BC2    │   DATA BC3    │
          ──┴───────────────┴───────────────┴───────────────┴───

The output frequency of this module is 280 MHz, 7 times 40 MHz. Only 5 TOBs per BC can be produced, so no tob will be transmitted in the last 2 clock cycles The output timing is represented in figure

            ┌──────┐      ┌──────┐      ┌
 CLK40:    ─┘      └──────┘      └──────┘
            ┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌
 CLK280:   ─┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘
            ┌┐            ┌┐            ┌
 Start:   ──┘└────────────┘└────────────┘
          ──┬─┬─┬─┬─┬─┬───┬─┬─┬─┬─┬─┬───┬
 TOB out:   │1│2│3│4│5│   │1│2│3│4│5│   │
          ──┴─┴─┴─┴─┴─┴───┴─┴─┴─┴─┴─┴───┴

A multicycle constraint of 2 is used to cross the clock domains from 40 to 200MHz and from 200 to 280 MHz.

Author

Francesco Gonnella

Definition at line 72 of file IPBusTopAlgoModule.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/IPBusTopAlgoModule.vhd