Top feature extracting algorithm module with IPBus interface. More...

Processes
BCN_sync_proc	( CLK280 )
Counter_280	( CLK280 )
Counter_200	( CLK200 )

Constants
N_CTRL	positive := 64
	Number of control IPBus reg.
N_STAT	positive := 64
	Number of status IPBus reg.
PHASE280	integer := 5
	Synchrnoisation phase between 200MHZ and 280MHz clocks.
PHASE200	integer := 6
	Synchrnoisation phase between 40MHZ and 200MHz clocks.

Signals
eg_ParWs	AlgoParameters ( 2 downto 0 )
	Ws condition thresholds.
eg_ParReta	AlgoParameters ( 2 downto 0 )
	Reta condition thresholds.
eg_ParHadron	AlgoParameters ( 2 downto 0 )
	Hadronic condition thresholds.
tau_ParJet	AlgoParameters ( 2 downto 0 )
	Tau Jet condition thresholds.
tau_ParFrac	AlgoParameters ( 2 downto 0 )
	Tau Frac condition thresholds.
eg_Control	AlgoRegister := ( others = > ' 0 ' )
tau_Control	AlgoRegister := ( others = > ' 0 ' )
eg_Status	AlgoRegister
tau_Status	AlgoRegister
glob_Position	AlgoRegister := ( others = > ' 0 ' )
	Bit 0 eFEX on edge, bit 1 eFEX on left edge.
glob_Control	AlgoRegister := ( others = > ' 0 ' )
glob_Status	AlgoRegister
debug_Status	AlgoRegisters ( 15 downto 0 )
debug_Control	AlgoRegisters ( 15 downto 0 )
NoiseThresholds	AlgoRegisters ( 29 downto 0 )
eg_Energy_threshold	DataWord
eg_Condition_threshold	DataWord
tau_Energy_threshold	DataWord
tau_Condition_threshold	DataWord
tau_BDT_min_energy_threshold	DataWord
FakeInput	AlgoInput
BCN280	std_logic_vector ( 11 downto 0 )
BCNOut	std_logic_vector ( 11 downto 0 )
BCN_to_output_ram	std_logic_vector ( 11 downto 0 )
BCN200	std_logic_vector ( 11 downto 0 )
FakeBCN	std_logic_vector ( 11 downto 0 )
EnableSpyBCN_eg	std_logic := ' 0 '
EnableSpyBCN_tau	std_logic := ' 0 '
AlgoDataInput	AlgoInput
FakeEgOutput	AlgoTriggerObjects ( OUTPUT_TOBS- 1 downto 0 )
FakeTauOutput	AlgoTriggerObjects ( OUTPUT_TOBS- 1 downto 0 )
EnableInputSpy	std_logic := ' 0 '
EnableOutputEgSpy	std_logic := ' 0 '
EnableOutputTauSpy	std_logic := ' 0 '
EnableFakeAlgoInput	std_logic := ' 0 '
EnableFakeTOBeg	std_logic := ' 0 '
EnableFakeTOBtau	std_logic := ' 0 '
ipb_to_slaves	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipb_from_slaves	ipb_rbus_array ( N_SLAVES- 1 downto 0 ) := ( others = > IPB_RBUS_NULL )
write_reg	ipb_reg_v ( N_STAT - 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
read_reg	ipb_reg_v ( N_CTRL - 1 downto 0 )
ParRamData	std_logic_vector ( PARAMETER_RAM_DATA_WIDTH- 1 downto 0 )
ParRamAddress	std_logic_vector ( 2 downto 0 )
Load	std_logic
IS_Data	TriggerTowerMatrix
IS_Thresholds_l0	AlgoWords ( 5 downto 0 )
IS_Thresholds_l1	AlgoWords ( 5 downto 0 )
IS_Thresholds_l2	AlgoWords ( 5 downto 0 )
IS_Thresholds_l3	AlgoWords ( 5 downto 0 )
IS_Thresholds_had_tile	AlgoWords ( 5 downto 0 )
IS_Thresholds_had_lar	AlgoWords ( 5 downto 0 )
TOB_Start	std_logic
TOB_Counter	std_logic_vector ( 2 downto 0 )
eg_TOBs	TriggerObjects_eg ( OUTPUT_TOBS- 1 downto 0 )
eg_in_TOBs	TriggerObjects_eg ( OUTPUT_TOBS- 1 downto 0 )
Input_TOBs_eg	AlgoTriggerObjects ( OUTPUT_TOBS- 1 downto 0 )
SerialSorterEgInput	AlgoTriggerObjects ( OUTPUT_TOBS- 1 downto 0 )
eg_sorted_TOBs	AlgoTriggerObjects ( OUTPUT_TOBS- 1 downto 0 )
eg_sorted_TOB_Start	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
tau_TOBs	TriggerObjects_tau ( OUTPUT_TOBS- 1 downto 0 )
tau_in_TOBs	TriggerObjects_tau ( OUTPUT_TOBS- 1 downto 0 )
Input_TOBs_tau	AlgoTriggerObjects ( OUTPUT_TOBS- 1 downto 0 )
SerialSorterTauInput	AlgoTriggerObjects ( OUTPUT_TOBS- 1 downto 0 )
tau_sorted_TOBs	AlgoTriggerObjects ( OUTPUT_TOBS- 1 downto 0 )
tau_sorted_TOB_Start	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
eg_tob_empty	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
tau_tob_empty	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
eg_xtob_valid	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
tau_xtob_valid	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
eg_DMC_b0	AlgoParameter
eg_DMC_b1	AlgoParameter
eg_DMC_b2	AlgoParameter
eg_DMC_b3	AlgoParameter
Load280	std_logic
Load200	std_logic
Count280	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
Count200	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
OutLoad	std_logic

Attributes
keep	string
max_fanout	integer
keep	signal is " true "
max_fanout	signal is 1000

Instantiations
load_generator	LoadGenerator <Entity LoadGenerator>
input_stage	AlgoInputStage <Entity AlgoInputStage>
top_algo_module	TopAlgoModule <Entity TopAlgoModule>
serialsorter_eg	SerialSorter <Entity SerialSorter>
serialsorter_tau	SerialSorter <Entity SerialSorter>
rate_monitor	AlgoRateMonitor <Entity AlgoRateMonitor>
ipbus_fabric	ipbus_fabric_sel
ipbus_algo_registers	ipbus_ctrlreg_v
ipbus_algo_parameter_ram	AlgoParameterRAM_wrapper <Entity AlgoParameterRAM_wrapper>
ipbus_input_ram	ipbus_inputRAM <Entity ipbus_inputRAM>
ipbus_output_eg_ram	ipbus_outputRAM_wrapper <Entity ipbus_outputRAM_wrapper>
ipbus_output_tau_ram	ipbus_outputRAM_wrapper <Entity ipbus_outputRAM_wrapper>
bcn_delay_internal	GeneralDelay <Entity GeneralDelay>
bcn_delay_to_readout	GeneralDelay <Entity GeneralDelay>

Detailed Description

Top feature extracting algorithm module with IPBus interface.

The feature extracting module runs at 200 MHz, i.e. 5 times faster than the BC frequency. So data belonging to a Bunch Crossing (BC) can be handled in 5 clock cycles. An eFEX FPGA handles 60 input Trigger Towers (TT) among which 40 are core towers, i.e. a TOB must be produced for each of them and 20 are used just as environment.

In order to produce 40 TOBs per BC, 40 independent Algorithm Cores (ACs) should process data in parallel. Thanks to the higher frequency, 8 ACs are enough to process data presented to the cores in 5 clock cycles. It is possible to handle a region of 0.7 Eta * 0.8 Phi.

In case the eFEX module is handling a border region in Eta, a number of environment-only TT must be used as core. This means that real data from the column at the far left end (or right) is not provided by the calorimeter. In this case, dummy data (e.g. all zeroes) are fed to the ACs. This module uses 2 clocks: 200 MHz and 280 MHz, plus a 40 MHz 12% duty cyle Load clock. The 200MHz, the Load and the 40MHz clocks must be in phase when the Load is high, as shown in figure.

            ┌───────┐       ┌───────┐       ┌───────┐       ┌───
 CLK40:    ─┘       └───────┘       └───────┘       └───────┘
            ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
 CLK200:   ─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─
            ┌┐              ┌┐              ┌┐              ┌┐
 Load:    ──┘└──────────────┘└──────────────┘└──────────────┘└──
          ──┬───────────────┬───────────────┬───────────────┬───
 Data:      │   DATA BC1    │   DATA BC2    │   DATA BC3    │
          ──┴───────────────┴───────────────┴───────────────┴───

The output frequency of this module is 280 MHz, 7 times 40 MHz. Only 5 TOBs per BC can be produced, so no tob will be transmitted in the last 2 clock cycles The output timing is represented in figure

            ┌──────┐      ┌──────┐      ┌
 CLK40:    ─┘      └──────┘      └──────┘
            ┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌
 CLK280:   ─┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘
            ┌┐            ┌┐            ┌
 Start:   ──┘└────────────┘└────────────┘
          ──┬─┬─┬─┬─┬─┬───┬─┬─┬─┬─┬─┬───┬
 TOB out:   │1│2│3│4│5│   │1│2│3│4│5│   │
          ──┴─┴─┴─┴─┴─┴───┴─┴─┴─┴─┴─┴───┴

A multicycle constraint of 2 is used to cross the clock domains from 40 to 200MHz and from 200 to 280 MHz.

Author: Francesco Gonnella

Definition at line 113 of file IPBusTopAlgoModule.vhd.

The documentation for this class was generated from the following file:

Algorithm/hdl/IPBusTopAlgoModule.vhd

Processes

Constants

Signals

Attributes

Instantiations

Detailed Description