IPBusTopAlgoModule.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
use work.ipbus_decode_efex_algorithm.all;
 
use work.DataTypes.all;
use work.AlgoDataTypes.all;
 
library ipbus_lib;
use ipbus_lib.ipbus_reg_types.all;
use ipbus_lib.ipbus.all;
 
library infrastructure_lib;
use infrastructure_lib.EfexDataFormats.all;
 
entity IPBusTopAlgoModule is
  generic (ENCODING_MODE   : integer;
           USE_INPUT_RAM   : boolean := false;
           EFEX_POSITION   : integer := 0;
           USE_OUTPUT_RAMS : boolean := false;
           FPGA            : integer := 1;
           EG_ALGO_VERSION : std_logic_vector(1 downto 0);           
           TAU_ALGO_VERSION : std_logic_vector(1 downto 0));
 
  port (CLK200           : in  std_logic;
        CLK280           : in  std_logic;
        IN_Load          : in  std_logic;
        ipb_clk          : in  std_logic;
        ipb_rst          : in  std_logic;
        ipb_in           : in  ipb_wbus;
        ipb_out          : out ipb_rbus;
        OUT_eFEXPosition : out std_logic_vector(31 downto 0);
 
        IN_Data      : in  AlgoInput;
        IN_BCN       : in  std_logic_vector(11 downto 0);
        OUT_eg_Sync  : out std_logic;
        OUT_eg_Valid : out std_logic_vector(OUTPUT_TOBS-1 downto 0);
 
        OUT_eg_TOB : out AlgoOutput;
 
        OUT_BCN_XTOB       : out std_logic_vector(11 downto 0);
        OUT_eg_sync_XTOB   : out std_logic;
        OUT_tau_sync_XTOB  : out std_logic;
        OUT_eg_XTOB        : out AlgoXOutput;
        OUT_tau_XTOB       : out AlgoXOutput;
        OUT_eg_Valid_XTOB  : out std_logic_vector(OUTPUT_TOBS-1 downto 0);
        OUT_tau_Valid_XTOB : out std_logic_vector(OUTPUT_TOBS-1 downto 0);
 
        OUT_BCN_TOB : out std_logic_vector(11 downto 0);
 
        OUT_tau_Sync  : out std_logic;
        OUT_tau_Valid : out std_logic_vector(OUTPUT_TOBS-1 downto 0);
        OUT_tau_TOB   : out AlgoOutput);
end IPBusTopAlgoModule;
 
architecture Behavioral of IPBusTopAlgoModule is
 
 
  constant N_CTRL : positive := 64;
  constant N_STAT : positive := 64;
 
  --Algorithm parameter
  signal eg_ParWs     : AlgoParameters(2 downto 0);
  signal eg_ParReta   : AlgoParameters(2 downto 0);
  signal eg_ParHadron : AlgoParameters(2 downto 0);
  signal tau_ParJet   : AlgoParameters(2 downto 0);
  signal tau_ParFrac  : AlgoParameters(2 downto 0);
 
 
  --Control and status registers
  signal eg_Control      : AlgoRegister := (others => '0');
  signal tau_Control     : AlgoRegister := (others => '0');
  signal eg_Status       : AlgoRegister;
  signal tau_Status      : AlgoRegister;
  signal glob_Position   : AlgoRegister := (others => '0');
  signal glob_Control    : AlgoRegister := (others => '0');
  signal glob_Status     : AlgoRegister;
  signal debug_Status    : AlgoRegisters(15 downto 0);
  signal debug_Control   : AlgoRegisters(15 downto 0);
  signal NoiseThresholds : AlgoRegisters(29 downto 0);
 
  signal eg_Energy_threshold    : DataWord;
  signal eg_Condition_threshold : DataWord;
 
  signal tau_Energy_threshold     : DataWord;
  signal tau_Condition_threshold  : DataWord;
  signal tau_BDT_min_energy_threshold : DataWord;
  --Spy memories signals:
  signal FakeInput : AlgoInput;
 
  signal BCN280, BCNOut, BCN_to_output_ram : std_logic_vector(11 downto 0);
  signal BCN200, FakeBCN                   : std_logic_vector(11 downto 0);
 
  signal EnableSpyBCN_eg, EnableSpyBCN_tau : std_logic := '0';
 
  signal AlgoDataInput : AlgoInput;
 
  signal FakeEgOutput, FakeTauOutput                            : AlgoTriggerObjects(OUTPUT_TOBS-1 downto 0);
  signal EnableInputSpy, EnableOutputEgSpy, EnableOutputTauSpy  : std_logic := '0';
  signal EnableFakeAlgoInput, EnableFakeTOBeg, EnableFakeTOBtau : std_logic := '0';
 
 
-- IPBus signals
  signal ipb_to_slaves   : ipb_wbus_array(N_SLAVES - 1 downto 0);
  signal ipb_from_slaves : ipb_rbus_array(N_SLAVES - 1 downto 0) := (others => IPB_RBUS_NULL);
 
  signal write_reg : ipb_reg_v(N_STAT - 1 downto 0) := (others => (others => '0'));
  signal read_reg  : ipb_reg_v(N_CTRL - 1 downto 0);
 
 
-- Parameter RAM signals
  signal ParRamData    : std_logic_vector(PARAMETER_RAM_DATA_WIDTH-1 downto 0);
  signal ParRamAddress : std_logic_vector(2 downto 0);
 
  signal Load : std_logic;
 
  signal IS_Data               : TriggerTowerMatrix;
  signal IS_Thresholds_l0       : AlgoWords(5 downto 0);
  signal IS_Thresholds_l1       : AlgoWords(5 downto 0);
  signal IS_Thresholds_l2       : AlgoWords(5 downto 0);
  signal IS_Thresholds_l3       : AlgoWords(5 downto 0);
  signal IS_Thresholds_had_tile : AlgoWords(5 downto 0);
  signal IS_Thresholds_had_lar  : AlgoWords(5 downto 0);
 
 
  signal TOB_Start            : std_logic;
  signal TOB_Counter          : std_logic_vector(2 downto 0);
  signal eg_TOBs              : TriggerObjects_eg(OUTPUT_TOBS-1 downto 0);
  signal eg_in_TOBs           : TriggerObjects_eg(OUTPUT_TOBS-1 downto 0);
  signal Input_TOBs_eg        : AlgoTriggerObjects(OUTPUT_TOBS-1 downto 0);
  signal SerialSorterEgInput  : AlgoTriggerObjects(OUTPUT_TOBS-1 downto 0);
  signal eg_sorted_TOBs       : AlgoTriggerObjects(OUTPUT_TOBS-1 downto 0);
  signal eg_sorted_TOB_Start  : std_logic_vector(OUTPUT_TOBS-1 downto 0);
  signal tau_TOBs             : TriggerObjects_tau(OUTPUT_TOBS-1 downto 0);
  signal tau_in_TOBs          : TriggerObjects_tau(OUTPUT_TOBS-1 downto 0);
  signal Input_TOBs_tau       : AlgoTriggerObjects(OUTPUT_TOBS-1 downto 0);
  signal SerialSorterTauInput : AlgoTriggerObjects(OUTPUT_TOBS-1 downto 0);
  signal tau_sorted_TOBs      : AlgoTriggerObjects(OUTPUT_TOBS-1 downto 0);
  signal tau_sorted_TOB_Start : std_logic_vector(OUTPUT_TOBS-1 downto 0);
 
  signal eg_tob_empty  : std_logic_vector(OUTPUT_TOBS-1 downto 0);
  signal tau_tob_empty : std_logic_vector(OUTPUT_TOBS-1 downto 0);
 
  signal eg_xtob_valid  : std_logic_vector(OUTPUT_TOBS-1 downto 0);
  signal tau_xtob_valid : std_logic_vector(OUTPUT_TOBS-1 downto 0);
 
 
  signal eg_DMC_b0, eg_DMC_b1, eg_DMC_b2, eg_DMC_b3 : AlgoParameter;
 
  signal Load280  : std_logic;
  signal Load200  : std_logic;
  signal Count280 : std_logic_vector(2 downto 0) := (others => '0');
  signal Count200 : std_logic_vector(2 downto 0) := (others => '0');
  signal OutLoad  : std_logic;
 
  constant PHASE280 : integer := 5;
  constant PHASE200 : integer := 6;
 
--  ####### attributes  ########
  attribute keep                          : string;
  attribute max_fanout                    : integer;
  attribute keep of eg_Control            : signal is "true";
  attribute max_fanout of eg_Control      : signal is 1000;
  attribute keep of tau_Control           : signal is "true";
  attribute max_fanout of tau_Control     : signal is 1000;
  attribute keep of glob_Control          : signal is "true";
  attribute max_fanout of glob_Control    : signal is 1000;
  attribute keep of debug_Control         : signal is "true";
  attribute max_fanout of debug_Control   : signal is 1000;
  attribute keep of glob_Position         : signal is "true";
  attribute max_fanout of glob_Position   : signal is 1000;
  attribute keep of NoiseThresholds       : signal is "true";
  attribute max_fanout of NoiseThresholds : signal is 1000;
 
begin
  LOAD_GENERATOR : entity work.LoadGenerator
    generic map(
      PHASE200 => PHASE200,
      PHASE280 => PHASE280)
    port map (
      IN_Load     => IN_Load,
      CLK200      => CLK200,
      CLK280      => CLK280,
      OUT_Load280 => Load280,
      OUT_Load200 => Load200);
 
-- Data spy MUX
  AlgoDataInput <= FakeInput when EnableFakeAlgoInput = '1' else IN_Data;
 
  THRESHOLD_FOR : for i in 0 to 5 generate
    IS_Thresholds_l0 (i)      <= NoiseThresholds(i*5+0)(9 downto 0);
    IS_Thresholds_l1 (i)      <= NoiseThresholds(i*5+1)(9 downto 0);
    IS_Thresholds_l2 (i)      <= NoiseThresholds(i*5+2)(9 downto 0);
    IS_Thresholds_l3 (i)      <= NoiseThresholds(i*5+3)(9 downto 0);
    IS_Thresholds_had_lar (i) <= NoiseThresholds(i*5+4)(9 downto 0);
    IS_Thresholds_had_tile(i) <= NoiseThresholds(i*5+4)(25 downto 16);
  end generate;
 
  INPUT_STAGE : entity work.AlgoInputStage
    generic map (ENCODING_MODE => ENCODING_MODE)
    port map (
      CLK200      => CLK200,
      IN_Load     => Load200,
      IN_Data     => AlgoDataInput,
      IN_Position => glob_Position,
      IN_BCN      => IN_BCN,
 
      IN_threshold_l0       => IS_Thresholds_l0,
      IN_threshold_l1       => IS_Thresholds_l1,
      IN_threshold_l2       => IS_Thresholds_l2,
      IN_threshold_l3       => IS_Thresholds_l3,
      IN_threshold_had_lar  => IS_Thresholds_had_lar,
      IN_threshold_had_tile => IS_Thresholds_had_tile,
 
      OUT_BCN_200 => BCN200,    -- BCN synced with 200 MHz clock
      OUT_Load    => Load,
      OUT_Data    => IS_Data);
 
  OUT_eFEXPosition <= glob_Position;
 
  BCN_sync_proc : process (CLK280)
  begin
    if rising_edge(CLK280) then
      if Count280 = "010" then  -- to meet multicycle 2 constraint between 200 nad 280
        if EnableFakeAlgoInput = '1' then
          BCN280 <= FakeBCN;    --Check THIS!!
        else
          BCN280 <= BCN200;
        end if;
 
      else
        BCN280 <= BCN280;
      end if;
    end if;
  end process BCN_sync_proc;
 
  TOP_ALGO_MODULE : entity work.TopAlgoModule
  generic map (
     EG_ALGO_VERSION => EG_ALGO_VERSION,
     TAU_ALGO_VERSION => TAU_ALGO_VERSION)
  port map (
      CLK200  => CLK200,
      IN_Load => Load,
 
      IN_Data => IS_Data,
 
      OUT_ParameterRAMaddress => ParRamAddress,
 
      IN_eg_ParWs     => eg_ParWs,
      IN_eg_ParReta   => eg_ParReta,
      IN_eg_ParHadron => eg_ParHadron,
 
      IN_eg_Energy_threshold => eg_Energy_threshold,
      IN_eg_Cond_threshold   => eg_Condition_threshold,
 
      IN_tau_Energy_threshold => tau_Energy_threshold,
      IN_tau_Cond_threshold   => tau_Condition_threshold,
      IN_tau_BDT_min_energy_threshold   => tau_BDT_min_energy_threshold,
 
      IN_ParDeadMat_b0 => eg_DMC_b0,
      IN_ParDeadMat_b1 => eg_DMC_b1,
      IN_ParDeadMat_b2 => eg_DMC_b2,
      IN_ParDeadMat_b3 => eg_DMC_b3,
 
      IN_eg_Control => eg_Control,
      OUT_eg_Status => eg_Status,
 
      IN_tau_ParJet  => tau_ParJet,
      IN_tau_ParFrac => tau_ParFrac,
 
 
      IN_tau_Control => tau_Control,
      OUT_tau_Status => tau_Status,
 
 
 
      IN_glob_Position => glob_Position,
      IN_glob_Control  => glob_Control,
      OUT_glob_Status  => glob_Status,
 
      OUT_TOB_Start   => TOB_Start,
      OUT_TOB_Counter => TOB_Counter,
 
      OUT_eg_TOB => eg_TOBs,
 
      OUT_tau_TOB => tau_TOBs);
 
  Counter_280 : process (CLK280)
  begin  -- process dd
    if rising_edge(CLK280) then
      if Load280 = '1' then     -- Reset the counter accordingly
        Count280 <= (others => '0');
      else
        Count280 <= std_logic_vector(unsigned(Count280)+1);
      end if;
    end if;
  end process;
 
  Counter_200 : process (CLK200)
  begin  -- process dd
    if rising_edge(CLK200) then
      if Load200 = '1' then     -- Reset the counter accordingly
        Count200 <= (others => '0');
      else
        Count200 <= std_logic_vector(unsigned(Count200)+1);
      end if;
    end if;
  end process;
 
 
 
  out_tob_for : for i in 0 to OUTPUT_TOBS-1 generate
 
    --Eta is given by the TOB counter
    --Phi is given by the index of this for
 
    eg_in_TOBs(i).Core          <= validate_core(eg_TOBs(i).Core);
    eg_in_TOBs(i).Position.Phi  <= std_logic_vector(to_unsigned(i, 3));
    tau_in_TOBs(i).Core         <= validate_core(tau_TOBs(i).Core);
    tau_in_TOBs(i).Position.Phi <= std_logic_vector(to_unsigned(i, 3));
 
    -- Change Eta numbering as a function of position
    -- When eFEX is on Left eta edge "11", eta goes from 0 to 4 (no + 1)
    -- When eFEX is on Right Eta edge "01", eta goes from 1 to 5
    -- When eFex is not on edge "x0", eta goes from 1 to 4
    tau_in_TOBs(i).Position.Eta <= TOB_Counter when glob_Position(1 downto 0) = "11" else std_logic_vector(unsigned(TOB_Counter) + 1);
    eg_in_TOBs(i).Position.Eta  <= TOB_Counter when glob_Position(1 downto 0) = "11" else std_logic_vector(unsigned(TOB_Counter) + 1);
 
    Input_TOBs_eg(i)  <= to_AlgoTriggerObject(eg_in_TOBs(i), FPGA);
    Input_TOBs_tau(i) <= to_AlgoTriggerObject(tau_in_TOBs(i), FPGA);
 
    SerialSorterEgInput(i)  <= FakeEgOutput(i)  when EnableFakeTOBeg = '1'  else Input_TOBs_eg(i);
    Serialsortertauinput(i) <= FakeTauOutput(i) when EnableFakeTOBtau = '1' else Input_TOBs_tau(i);
 
    SerialSorter_eg : entity work.SerialSorter
      port map (
        clk       => CLK200,
        clk_out   => CLK280,
        IN_Load   => Load280,
        IN_Clear  => TOB_Start,
        IN_Data   => SerialSorterEgInput(i),
        OUT_Start => eg_sorted_TOB_Start(i),
        OUT_Data  => eg_sorted_TOBs(i));
 
    SerialSorter_tau : entity work.SerialSorter
      port map (
        clk       => CLK200,
        clk_out   => CLK280,
        IN_Load   => Load280,
        IN_Clear  => TOB_Start,
        IN_Data   => SerialSorterTauInput(i),
        OUT_Start => tau_sorted_TOB_Start(i),
        OUT_Data  => tau_sorted_TOBs(i));
  end generate out_tob_for;
 
  valid_for : for i in OUTPUT_TOBS-1 downto 0 generate
    OUT_eg_Valid(i)  <= is_valid_TOB(eg_sorted_TOBs(i));
    OUT_tau_Valid(i) <= is_valid_TOB(tau_sorted_TOBs(i));
  end generate valid_for;
  -- TOBS to be sent out of this module to parallel sorting *280
  OUT_eg_Sync  <= eg_sorted_TOB_Start(0);   -- should be done better, what about
  OUT_tau_Sync <= tau_sorted_TOB_Start(0);  -- the other signals?
  OUT_eg_TOB   <= to_AlgoOutput(eg_sorted_TOBs);
  OUT_tau_TOB  <= to_AlgoOutput(tau_sorted_TOBs);
 
 
  -- XTOBS to be sent to out of this module to readout @200
  OUT_tau_Sync_XTOB <= TOB_Start;
  OUT_eg_Sync_XTOB  <= TOB_Start;
  valid_xtob_for : for i in OUTPUT_TOBS-1 downto 0 generate
    eg_xtob_valid(i)      <= is_valid_core(eg_in_TOBS(i).Core);  --this goes to rate monitor
    tau_xtob_valid(i)     <= is_valid_core(tau_in_TOBS(i).Core);
    OUT_eg_Valid_XTOB(i)  <= eg_xtob_valid(i);
    OUT_tau_Valid_XTOB(i) <= tau_xtob_valid(i);
  end generate;
  OUT_eg_XTOB  <= to_AlgoXOutput(eg_in_TOBS, FPGA);
  OUT_tau_XTOB <= to_AlgoXOutput(tau_in_TOBs, FPGA);
 
  OUT_BCN_XTOB <= BCN_to_output_RAM;
 
  RATE_MONITOR : entity work.AlgoRateMonitor
    port map (
      ipb_clk => ipb_clk,
      ipb_rst => ipb_rst,
      ipb_in  => ipb_to_slaves(N_SLV_ALGO_RATE_MONITOR),
      ipb_out => ipb_from_slaves(N_SLV_ALGO_RATE_MONITOR),
 
      clk    => clk200,
      IN_BCN => BCN_to_output_RAM,  --this is not used inside the block
 
      IN_synch => TOB_Start,
 
      IN_eta => eg_in_TOBS(0).Position.Eta,
 
      IN_eg_energies       => (7 => eg_in_TOBS(7).Core.Energy, 6 => eg_in_TOBS(6).Core.Energy, 5 => eg_in_TOBS(5).Core.Energy, 4 => eg_in_TOBS(4).Core.Energy,
                         3 => eg_in_TOBS(3).Core.Energy, 2 => eg_in_TOBS(2).Core.Energy, 1 => eg_in_TOBS(1).Core.Energy, 0 => eg_in_TOBS(0).Core.Energy),
      IN_eg_valids         => eg_xtob_valid,
 
      IN_tau_energies       => (7 => tau_in_TOBS(7).Core.Energy, 6 => tau_in_TOBS(6).Core.Energy, 5 => tau_in_TOBS(5).Core.Energy, 4 => tau_in_TOBS(4).Core.Energy,
                          3 => tau_in_TOBS(3).Core.Energy, 2 => tau_in_TOBS(2).Core.Energy, 1 => tau_in_TOBS(1).Core.Energy, 0 => tau_in_TOBS(0).Core.Energy),
      IN_tau_valids         => tau_xtob_valid
 
      );
 
  IPBUS_FABRIC : entity ipbus_lib.ipbus_fabric_sel
    generic map (
      NSLV      => N_SLAVES,                             --defined in ipbus_sel_address_table_ALGO
      SEL_WIDTH => IPBUS_SEL_WIDTH)
    port map (
      sel => ipbus_sel_efex_algorithm(ipb_in.ipb_addr),  --function defined in ipbus_sel_address_table_ALGO
 
      ipb_in          => ipb_in,
      ipb_out         => ipb_out,
      ipb_to_slaves   => ipb_to_slaves,
      ipb_from_slaves => ipb_from_slaves);
 
  IPBUS_ALGO_REGISTERS : entity ipbus_lib.ipbus_ctrlreg_v
    generic map (
      N_CTRL => N_CTRL,         --number of control reg
      N_STAT => N_STAT)         --number of status reg
    port map (
      clk       => ipb_clk,
      reset     => ipb_rst,
      ipbus_in  => ipb_to_slaves(N_SLV_ALGO_REGISTERS),
      ipbus_out => ipb_from_slaves(N_SLV_ALGO_REGISTERS),
      d         => write_reg,
      q         => read_reg,
--    qmask     => (others => '0'),
      stb       => open);
 
  IPBUS_ALGO_PARAMETER_RAM : entity work.AlgoParameterRAM_wrapper
    port map (
      clk_ipb => ipb_clk,
      rst     => ipb_rst,
      ipb_in  => ipb_to_slaves(N_SLV_ALGO_PARAMETER_RAM),
      ipb_out => ipb_from_slaves(N_SLV_ALGO_PARAMETER_RAM),
      rclk    => CLK200,
      we      => '0',
      q       => ParRamData,
      addr    => ParRamAddress);
 
  INPUT_RAM_IF : if USE_INPUT_RAM generate
    IPBUS_INPUT_RAM : entity work.ipbus_inputRAM
      port map (
        clk_ipb => ipb_clk,
        rst     => ipb_rst,
        ipb_in  => ipb_to_slaves(N_SLV_ALGO_INPUT_RAM),    --have to see how it is
        ipb_out => ipb_from_slaves(N_SLV_ALGO_INPUT_RAM),  --  generated by ipbus
 
        rclk    => CLK200,
        Load    => Load200,
        BCNIn   => IN_BCN,
        AlgoIn  => IN_Data,         -- connected to IN_Data used for data spy
        we      => EnableInputSpy,  -- enabled in case of data spy
        BCNOut  => FakeBCN,
        AlgoOut => FakeInput);      -- used to feed data into Algorithm block
 
  else generate
    ipb_from_slaves(N_SLV_ALGO_INPUT_RAM) <= IPB_RBUS_NULL;
    FakeBCN                               <= (others => '0');
    FakeInput                             <= ZERO_ALGO_INPUT;
  end generate;
 
 
  OUTPUT_RAM_IF : if USE_OUTPUT_RAMS generate
 
    IPBUS_OUTPUT_EG_RAM : entity work.ipbus_outputRAM_wrapper
      port map (
        clk_ipb => ipb_clk,
        rst     => ipb_rst,
        ipb_in  => ipb_to_slaves(N_SLV_ALGO_OUTPUT_EG_RAM),    --have to see how it is
        ipb_out => ipb_from_slaves(N_SLV_ALGO_OUTPUT_EG_RAM),  --  generated by ipbus
 
        BCNIn    => BCN_to_output_ram,
        SpyBCNIn => EnableSpyBCN_eg,
 
        rclk    => CLK200,
        Sync    => TOB_Start,
        AlgoIn  => to_AlgoOutput(Input_TOBs_eg),
        we      => EnableOutputEgSpy,
        AlgoOut => FakeEgOutput);
 
    IPBUS_OUTPUT_TAU_RAM : entity work.ipbus_outputRAM_wrapper
      port map (
        clk_ipb => ipb_clk,
        rst     => ipb_rst,
        ipb_in  => ipb_to_slaves(N_SLV_ALGO_OUTPUT_TAU_RAM),    --have to see how it is
        ipb_out => ipb_from_slaves(N_SLV_ALGO_OUTPUT_TAU_RAM),  --  generated by ipbus
 
        BCNIn    => BCN_to_output_ram,
        SpyBCNIn => EnableSpyBCN_tau,
 
        rclk    => CLK200,
        Sync    => TOB_Start,
        AlgoIn  => to_AlgoOutput(Input_TOBs_tau),
        we      => EnableOutputTauSpy,
        AlgoOut => FakeTauOutput);
  else generate
    ipb_from_slaves(N_SLV_ALGO_OUTPUT_EG_RAM)  <= IPB_RBUS_NULL;
    ipb_from_slaves(N_SLV_ALGO_OUTPUT_TAU_RAM) <= IPB_RBUS_NULL;
    FakeEgOutput                               <= (others => (others => '0'));
    FakeTauOutput                              <= (others => (others => '0'));
  end generate;
 
 
  BCN_Delay_internal : entity infrastructure_lib.GeneralDelay
    generic map (
      delay => 12,
      size  => 12)
    port map (
      clk      => CLk200,
      data_in  => BCN200,
      data_out => BCN_to_output_ram);
 
 
  BCN_Delay_to_Readout : entity infrastructure_lib.GeneralDelay
    generic map (
      delay => 24,
      size  => 12)
    port map (
      clk      => CLk280,
      data_in  => BCN280,
      data_out => BCNOut);
 
  OUT_BCN_TOB <= BCNOut;
 
-- Algor register funcionality
  EnableFakeAlgoInput <= glob_Control(0);
  EnableFakeTOBeg     <= eg_Control(0);
  EnableFakeTOBtau    <= tau_Control(0);
 
 
  EnableInputSpy     <= glob_Control(1);
  EnableOutputEgSpy  <= eg_Control(1);
  EnableOutputTauSpy <= tau_Control(1);
 
  EnableSpyBCN_eg  <= eg_Control(2);
  EnableSpyBCN_tau <= tau_Control(2);
 
 
-- Algorithm registers connection
  eg_Control         <= read_reg(00);
  tau_Control        <= read_reg(01);
  glob_Control       <= read_reg(02);
  glob_Position      <= read_reg(03) when EFEX_POSITION = 0 else f_efex_position(FPGA, EFEX_POSITION);
  
  
  thr_connection: for i in 29 downto 0 generate
    NoiseThresholds(i) <= read_reg(i+8);
  end generate;
  
  write_reg(0) <= glob_Position;
  write_reg(1) <= x"0000000" & '0' & TOB_Counter;
  write_reg(2) <= x"0000000" & '0' & Count280;
  write_reg(3) <= (others => '0');
 
-------------------------------------------------------------------------------
-- ALGORITHM PARAMETER CONNECTION
-------------------------------------------------------------------------------
-- Electromagnetic
  eg_ParReta(0) <= ParRamData(7 downto 0);  --ipbus word 0
  eg_ParReta(1) <= ParRamData(15 downto 8);
  eg_ParReta(2) <= ParRamData(23 downto 16);
  eg_DMC_b0     <= ParRamData(31 downto 24);
 
  eg_ParWs(0) <= ParRamData(7+32 downto 0+32);  --ipbus word 1
  eg_ParWs(1) <= ParRamData(15+32 downto 8+32);
  eg_ParWs(2) <= ParRamData(23+32 downto 16+32);
  eg_DMC_b1   <= ParRamData(31+32 downto 24+32);
 
  eg_ParHadron(0) <= ParRamData(7+64 downto 0+64);  --ipbus word 2
  eg_ParHadron(1) <= ParRamData(15+64 downto 8+64);
  eg_ParHadron(2) <= ParRamData(23+64 downto 16+64);
  eg_DMC_b2       <= ParRamData(31+64 downto 24+64);
 
  eg_Energy_threshold    <= ParRamData(15+96 downto 0+96);  --ipbus word 3
  eg_Condition_threshold <= ParRamData(31+96 downto 16+96);
 
  tau_ParFrac(0) <= ParRamData(7+128 downto 0+128);  --ipbus word 4
  tau_ParFrac(1) <= ParRamData(15+128 downto 8+128);
  tau_ParFrac(2) <= ParRamData(23+128 downto 16+128);
  eg_DMC_b3      <= ParRamData(31+128 downto 24+128);
 
-- Tau
  tau_ParJet(0) <= ParRamData(7+160 downto 0+160);  --ipbus word 5
  tau_ParJet(1) <= ParRamData(15+160 downto 8+160);
  tau_ParJet(2) <= ParRamData(23+160 downto 16+160);
  -- 8 unused bits
 
  tau_Energy_threshold     <= ParRamData(15+192 downto 0+192);  -- ipbus word 6
  tau_Condition_threshold  <= ParRamData(31+192 downto 16+192);
 
  tau_BDT_min_energy_threshold <= ParRamData(15+224 downto 0+224); -- ipbus word 7
  -- 16 unused bits
 
end architecture;