AlgoInputStage.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
use work.DataTypes.all;
use work.AlgoDataTypes.all;
 
entity AlgoInputStage is
  generic(ENCODING_MODE : integer);
  port (CLK200      : in std_logic;
        IN_Load     : in std_logic;
        IN_Data     : in AlgoInput;
        IN_Position : in AlgoRegister;
        IN_BCN      : in std_logic_vector(11 downto 0);
 
        IN_threshold_l0       : in AlgoWords(INPUT_COLUMNS-1 downto 0);
        IN_threshold_l1       : in AlgoWords(INPUT_COLUMNS-1 downto 0);
        IN_threshold_l2       : in AlgoWords(INPUT_COLUMNS-1 downto 0);
        IN_threshold_l3       : in AlgoWords(INPUT_COLUMNS-1 downto 0);
        IN_threshold_had_lar  : in AlgoWords(INPUT_COLUMNS-1 downto 0);
        IN_threshold_had_tile : in AlgoWords(INPUT_COLUMNS-1 downto 0);
 
        OUT_Load    : out std_logic;
        OUT_BCN_200 : out std_logic_vector(11 downto 0);
        OUT_Data    : out TriggerTowerMatrix
        );
end AlgoInputStage;
 
architecture Behavioral of AlgoInputStage is
  signal InData                : AlgoInput;
  signal OutData               : TriggerTowerMatrix;
  signal Load_i, Load_d        : std_logic;
  signal BCN_i, BCN_d, BCN_200 : std_logic_vector(11 downto 0);
 
  signal had_position : std_logic_vector(2 downto 0);
  signal is_tile      : std_logic_vector(INPUT_ROWS*INPUT_COLUMNS-1 downto 0);
 
 
  signal hadronic_threshold : array_std_logic_vector(INPUT_ROWS*INPUT_COLUMNS-1 downto 0)(INPUT_DATA_WIDTH-1 downto 0);
 
--  ####### Mark signals  ########
 
  attribute keep                   : string;
  attribute max_fanout             : integer;
  attribute keep of OUT_Load       : signal is "true";
  attribute max_fanout of OUT_Load : signal is 50;
 
--   #######################################
 
begin
  Load_i       <= IN_Load;
  BCN_i        <= IN_BCN;
  had_position <= IN_Position(HADRONIC_POSITION_BIT_END downto HADRONIC_POSITION_BIT_START);
 
  --InData <= IN_DATA when IN_BCN(0) < IN_align_frame_BCN_min or IN_BCN(0) > IN_align_frame_BCN_max else ZERO_ALGO_INPUT;
  InData <= IN_DATA;            --temporary fix
 
  column_for : for i in 0 to INPUT_COLUMNS - 1 generate
    row_for : for j in 0 to INPUT_ROWS - 1 generate
 
      layer0_for : for k in 0 to LAYER0-1 generate
        EnergyConverter0 : entity work.EnergyConverter
          generic map (ENCODING_MODE => ENCODING_MODE)
          port map (
            clk          => CLK200,
            is_hadronic  => '0',
            IN_threshold => IN_threshold_l0(i),
            IN_Load      => Load_i,
            IN_Data      => InData(i)(j).Layer0(k),
            OUT_Data     => OutData(i)(j).Layer0(k));
      end generate layer0_for;
 
      layer1_for : for k in 0 to LAYER1-1 generate
        EnergyConverter1 : entity work.EnergyConverter
          generic map (ENCODING_MODE => ENCODING_MODE)
          port map (
            clk          => CLK200,
            is_hadronic  => '0',
            IN_threshold => IN_threshold_l1(i),
            IN_Load      => Load_i,
            IN_Data      => InData(i)(j).Layer1(k),
            OUT_Data     => OutData(i)(j).Layer1(k));
      end generate layer1_for;
 
      layer2_for : for k in 0 to LAYER2-1 generate
        EnergyConverter2 : entity work.EnergyConverter
          generic map (ENCODING_MODE => ENCODING_MODE)
          port map (
            clk          => CLK200,
            is_hadronic  => '0',
            IN_threshold => IN_threshold_l2(i),
            IN_Load      => Load_i,
            IN_Data      => InData(i)(j).Layer2(k),
            OUT_Data     => OutData(i)(j).Layer2(k));
      end generate layer2_for;
 
      layer3_for : for k in 0 to LAYER3-1 generate
        EnergyConverter3 : entity work.EnergyConverter
          generic map (ENCODING_MODE => ENCODING_MODE)
          port map (
            clk          => CLK200,
            is_hadronic  => '0',
            IN_threshold => IN_threshold_l3(i),
            IN_Load      => Load_i,
            IN_Data      => InData(i)(j).Layer3(k),
            OUT_Data     => OutData(i)(j).Layer3(k));
      end generate layer3_for;
 
      LAR_OR_TILE_IF : if i = 0 or i = 1 generate
        -- First to columns should be Lar (is_tile=0) in position 1,3,4
        is_tile(i*INPUT_ROWS+j)            <= '0'                  when had_position = "001" or had_position = "011" or had_position = "100" else '1';
        hadronic_threshold(i*INPUT_ROWS+j) <= IN_threshold_had_lar(i) when had_position = "001" or had_position = "011" or had_position = "100"
                                              else IN_threshold_had_tile(i);
 
      elsif i = 4 or i = 5 generate
        --Last two columns should be LAr (is_tile = 0) in position 2,3,4
        is_tile(i*INPUT_ROWS+j) <= '0' when had_position = "010" or had_position = "011" or had_position = "100" else '1';
 
        hadronic_threshold(i*INPUT_ROWS+j) <= IN_threshold_had_lar(i) when had_position = "010" or had_position = "011" or had_position = "100"
                                              else IN_threshold_had_tile(i);
 
      else generate
        --All other columns should be Lar in position 3,4
        is_tile(i*INPUT_ROWS+j) <= '0' when had_position = "011" or had_position = "100" else '1';
 
        hadronic_threshold(i*INPUT_ROWS+j) <= IN_threshold_had_lar(i) when had_position = "011" or had_position = "100"
                                              else IN_threshold_had_tile(i);
 
      end generate;
 
 
      EnergyConverterH : entity work.EnergyConverter
        generic map (ENCODING_MODE => ENCODING_MODE)
        port map (
          clk          => CLK200,
          is_hadronic  => is_tile(i*INPUT_ROWS+j),
          IN_threshold => hadronic_threshold(i*INPUT_ROWS+j),
          IN_Load      => Load_i,
          IN_Data      => InData(i)(j).Hadron(0),
          OUT_Data     => OutData(i)(j).Hadron(0));
 
    end generate row_for;
  end generate column_for;
 
  OUT_Data <= OutData;
 
  process (CLK200)
  begin
    if rising_edge(CLK200) then
      Load_d   <= Load_i;
      OUT_Load <= Load_d;
    end if;
  end process;
 
  process (CLK200)
  begin
    if rising_edge(CLK200) then
      if Load_i = '1' then
        BCN_200 <= BCN_i;
      else
        BCN_200 <= BCN_200;
      end if;
      BCN_d <= BCN_200;
    end if;
  end process;
 
  OUT_BCN_200 <= BCN_d;
 
end Behavioral;